Resolve the catch-22 of igt needing a stable number and patches first
needing testcases by reserving the interface number up-front.
Requested-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Signed-off-by: Daniel Vetter <daniel.vetter@xxxxxxxx>
---
include/uapi/drm/i915_drm.h | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index a1a7b6b..96b86f8 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -768,8 +768,32 @@ struct drm_i915_gem_busy {
__u32 busy;
};
+/**
+ * I915_CACHING_NONE
+ *
+ * GPU access is not coherent with cpu caches. Default for machines without a
+ * LLC.
+ */
#define I915_CACHING_NONE 0
+/**
+ * I915_CACHGING_CACHED
+ *
+ * GPU access is coherent with cpu caches and furthermore the data is cached in
+ * last-level caches shared between cpu cores and the gpu GT. Default on
+ * machines with HAS_LLC.
+ */
#define I915_CACHING_CACHED 1
+/**
+ * I915_CACHING_DISPLAY
+ *
+ * Special GPU which is coherent with the scanout engines. Transparently falls
+ * back to I915_CACHING_NONE on platforms where not special cache mode (like
+ * write-through or gfdt flushing) is available. The kernel automatically sets
+ * this mode when using a buffer as a scanout target. Userspace can manually set
+ * this mode to avoid a costly stall and clflush in the hotpath of drawing the
+ * first frame.
+ */
+#define I915_CACHING_CACHED 2
struct drm_i915_gem_caching {
/**
--
1.8.4.rc1
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