This patch series aims to enable the YCbCr420 format
for DSC. Changes are mostly compute params related for
hdmi,dp and dsi along with the addition of new rc_tables
for native_420 and corresponding changes to macros used to
fetch them.
---v2
-add fields missed for vdsc_cfg [Vandita]
-add corresponding registers and writing to the [Vandita]
---v3
-add 11 bit left shift missed in nsl_bpg_offset calculation
---v4
-add display version check before writing in new pps register
---v5
-add helper to check if sink supports given format with DSC
-add debugfs entry to enforce DSC with YCbCr420 format only
--v6
-add patch to check dsc slice design requirement [Vandita]
--v7
-fix function name to intel_slice_dimensions_valid [Jani]
-remove full bspec link just add the ref number [Jani]
-remove patches for debug fs will float them as a seprate series
-Add more description for YUV420 Enablement [Vandita]
--v8
-fix slice width and height 2's multiple check
-fix minimum pixel requirement in slice check
Ankit Nautiyal (2):
drm/dp_helper: Add helper to check if the sink supports given format
with DSC
drm/i915/dp: Check if DSC supports the given output_format
Suraj Kandpal (4):
drm/i915: Adding the new registers for DSC
drm/i915: Enable YCbCr420 for VDSC
drm/i915: Fill in native_420 field
drm/i915/vdsc: Check slice design requirement
drivers/gpu/drm/i915/display/icl_dsi.c | 2 -
drivers/gpu/drm/i915/display/intel_dp.c | 33 +++-
.../gpu/drm/i915/display/intel_qp_tables.c | 187 ++++++++++++++++--
.../gpu/drm/i915/display/intel_qp_tables.h | 4 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 106 +++++++++-
drivers/gpu/drm/i915/i915_reg.h | 28 +++
include/drm/display/drm_dp_helper.h | 7 +
7 files changed, 345 insertions(+), 22 deletions(-)
--
2.25.1
