> > > > Note, KVM may also restrict the mapping size for reasons that aren't > > > > relevant to KVMGT, e.g. for KVM's iTLB multi-hit workaround or if the gfn > > > Will iTLB multi-hit affect DMA? > > > > I highly doubt it, I can't imagine an IOMMU would have a dedicated instruction > > TLB :-) > I can double check it with IOMMU hardware experts. > But if DMA would tamper instruction TLB, it should have been reported > as an issue with normal VFIO pass-through? hi Sean, This is the feedback: - CPU Instruction TLB is only filled when CPU fetches an instruction. - IOMMU uses IOTLB to cache IOVA translation. A remapping hardware may implement multiple IOTLBs, and some of these may be for special purposes, e.g., only for instruction fetches. There is no way for software to be aware that multiple translations for smaller pages have been used for a large page. If software modifies the paging structures so that the page size used for a 4-KByte range of input-addresses changes, the IOTLBs may subsequently contain multiple translations for the address range (one for each page size). A reference to a input-address in the address range may use any of these translations. Which translation is used may vary from one execution to another, and the choice may be implementation-specific. - Theres no similar bug related to DMA requests for instruction fetch hitting multiple IOTLB entries reported in IOMMU side. The X bit in IOMMU paging structure is to be removed in future and is currently always unset. Thanks Yan
