---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ring_submission.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++----
5 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index ef45dfc6adae..25a982925cf2 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1614,7 +1614,7 @@ static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask)
}
/*
- * Wa_22011802037
+ * Wa_22011802037 - In addition to stopping the cs, we need to wait for any
* pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The
* pending status is indicated by bits[13:9] (masked by bits[29:25]) in the
* MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 9f232c743ee7..1510255f6a50 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2989,7 +2989,7 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine)
intel_engine_stop_cs(engine);
/*
- * Wa_22011802037
+ * Wa_22011802037 - In addition to stopping the cs, we need
* to wait for any pending mi force wakeups
*/
if (IS_GRAPHICS_VER(engine->i915, 11, 12))
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index f59d38a5e2a0..b3ea634958d1 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -613,7 +613,7 @@ static int gen8_reset_engines(struct intel_gt *gt,
}
/*
- * Wa_22011100796
+ * Wa_22011100796 - whenever Full soft reset is required,
* reset all individual engines firstly, and then do a full soft reset.
*
* This is best effort, so ignore any error from the initial reset.
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 704b50467ce3..5414df579341 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -317,9 +317,9 @@ static void reset_prepare(struct intel_engine_cs *engine)
* Thus assume it is best to stop engines on all gens
* where we have a gpu reset.
*
- * WaKBLVECSSemaphoreWaitPoll
+ * WaKBLVECSSemaphoreWaitPoll - on ALL_ENGINES
*
- * WaMediaResetMainRingCleanup
+ * WaMediaResetMainRingCleanup - presumably
* WaClearRingBufHeadRegAtInit
*
* FIXME: Wa for more modern gens needs to be validated
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index edfa7d98a409..b01af1ed2382 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1425,7 +1425,7 @@ tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
SUBSLICE_UNIT_LEVEL_CLKGATE2,
CPSSUNIT_CLKGATE_DIS);
- /* Wa_1607087056 */
+ /* Wa_1607087056 - also know as BUG:1409180338 */
if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
wa_write_or(wal,
GEN11_SLICE_UNIT_LEVEL_CLKGATE,
@@ -2318,7 +2318,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
FORCE_1_SUB_MESSAGE_PER_FRAGMENT);
}
- /* Wa_1308578152 */
+ /* Wa_1308578152 - when first gslice is fused off */
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) &&
needs_wa_1308578152(engine)) {
wa_masked_dis(wal, GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON,
@@ -2417,8 +2417,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
/*
- * Wa_1606679103
- * (see also Wa_1606682166
+ * Wa_1606679103 - see also Wa_1606682166
*/
wa_write_or(wal,
GEN7_SARCHKMD,
--
2.39.0
