On Thu, 1 Aug 2013 14:12:22 -0700
Furquan Shaikh <furquan@xxxxxxxxxx> wrote:
> @@ -1282,6 +1283,13 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
> flags |= DRM_MODE_FLAG_NVSYNC;
>
> pipe_config->adjusted_mode.flags |= flags;
> +
> + if (port == PORT_A) {
> + if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
> + pipe_config->port_clock = 162000;
> + else
> + pipe_config->port_clock = 270000;
> + }
Sorry Furquan, I should have checked this earlier, I knew it was too
good to be true. :)
On HSW, DP_A is actually DDI_BUF_CTL, and it has a different layout
than the old DP_A reg. Like Daniel said, doing it the old way is
invalid on HSW. It might work in your configs, but I think that's just
coincidence, since bit 16 is the port reversal bit on HSW, not the
clock freq.
To get the clock freq, you need to look at 0x45020 to find the refclk,
then look at the WRPLL_CTL for the pipe to get the dividers. That's
what Daniel meant when he asked for a full "clock_get" function. It's
only a little more complicated, but you'll need docs for it. Charlie
Huang ought to be able to get you the NDA docs that should have the
info you need.
Thanks,
--
Jesse Barnes, Intel Open Source Technology Center
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