On Thu, Aug 01, 2013 at 04:18:39PM +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> For calculating watermarks we want to know whether sprites are
> scaled. Pass that information to update_sprite_watermarks() so that
> eventually we may do some watermark pre-computing.
>
> v2: Use "enabled" consistently, fix commit msg
>
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Oops, already merged v1. Please extract the fixup again and resubmit ;-)
-Daniel
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_drv.h | 7 ++++---
> drivers/gpu/drm/i915/intel_pm.c | 15 ++++++++-------
> drivers/gpu/drm/i915/intel_sprite.c | 11 +++++++----
> 4 files changed, 20 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 82ea281..fe466bc 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -361,7 +361,7 @@ struct drm_i915_display_funcs {
> void (*update_wm)(struct drm_device *dev);
> void (*update_sprite_wm)(struct drm_device *dev, int pipe,
> uint32_t sprite_width, int pixel_size,
> - bool enable);
> + bool enabled, bool scaled);
> void (*modeset_global_resources)(struct drm_device *dev);
> /* Returns the active state of the crtc, and if the crtc is active,
> * fills out the pipe-config with the hw state. */
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 474797b..ed33976 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -349,7 +349,8 @@ struct intel_plane {
> * for the watermark calculations. Currently only Haswell uses this.
> */
> struct {
> - bool enable;
> + bool enabled;
> + bool scaled;
> uint8_t bytes_per_pixel;
> uint32_t horiz_pixels;
> } wm;
> @@ -770,8 +771,8 @@ extern void intel_ddi_init(struct drm_device *dev, enum port port);
> /* For use by IVB LP watermark workaround in intel_sprite.c */
> extern void intel_update_watermarks(struct drm_device *dev);
> extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
> - uint32_t sprite_width,
> - int pixel_size, bool enable);
> + uint32_t sprite_width, int pixel_size,
> + bool enabled, bool scaled);
>
> extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
> unsigned int tiling_mode,
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0a5ba92..5a008d1 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2388,7 +2388,7 @@ static void hsw_compute_wm_parameters(struct drm_device *dev,
> pipe = intel_plane->pipe;
> p = ¶ms[pipe];
>
> - p->sprite_enabled = intel_plane->wm.enable;
> + p->sprite_enabled = intel_plane->wm.enabled;
> p->spr_bytes_per_pixel = intel_plane->wm.bytes_per_pixel;
> p->spr_horiz_pixels = intel_plane->wm.horiz_pixels;
>
> @@ -2616,7 +2616,7 @@ static void haswell_update_wm(struct drm_device *dev)
>
> static void haswell_update_sprite_wm(struct drm_device *dev, int pipe,
> uint32_t sprite_width, int pixel_size,
> - bool enable)
> + bool enabled, bool scaled)
> {
> struct drm_plane *plane;
>
> @@ -2624,7 +2624,8 @@ static void haswell_update_sprite_wm(struct drm_device *dev, int pipe,
> struct intel_plane *intel_plane = to_intel_plane(plane);
>
> if (intel_plane->pipe == pipe) {
> - intel_plane->wm.enable = enable;
> + intel_plane->wm.enabled = enabled;
> + intel_plane->wm.scaled = scaled;
> intel_plane->wm.horiz_pixels = sprite_width + 1;
> intel_plane->wm.bytes_per_pixel = pixel_size;
> break;
> @@ -2712,7 +2713,7 @@ sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
>
> static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
> uint32_t sprite_width, int pixel_size,
> - bool enable)
> + bool enabled, bool scaled)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
> @@ -2720,7 +2721,7 @@ static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
> int sprite_wm, reg;
> int ret;
>
> - if (!enable)
> + if (!enabled)
> return;
>
> switch (pipe) {
> @@ -2835,13 +2836,13 @@ void intel_update_watermarks(struct drm_device *dev)
>
> void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
> uint32_t sprite_width, int pixel_size,
> - bool enable)
> + bool enabled, bool scaled)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> if (dev_priv->display.update_sprite_wm)
> dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
> - pixel_size, enable);
> + pixel_size, enabled, scaled);
> }
>
> static struct drm_i915_gem_object *
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 55bdf70..069155f 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -114,7 +114,8 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_framebuffer *fb,
> crtc_w--;
> crtc_h--;
>
> - intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true);
> + intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true,
> + src_w != crtc_w || src_h != crtc_h);
>
> I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
> I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
> @@ -268,7 +269,8 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
> crtc_w--;
> crtc_h--;
>
> - intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true);
> + intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true,
> + src_w != crtc_w || src_h != crtc_h);
>
> /*
> * IVB workaround: must disable low power watermarks for at least
> @@ -336,7 +338,7 @@ ivb_disable_plane(struct drm_plane *plane)
>
> dev_priv->sprite_scaling_enabled &= ~(1 << pipe);
>
> - intel_update_sprite_watermarks(dev, pipe, 0, 0, false);
> + intel_update_sprite_watermarks(dev, pipe, 0, 0, false, false);
>
> /* potentially re-enable LP watermarks */
> if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled)
> @@ -456,7 +458,8 @@ ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
> crtc_w--;
> crtc_h--;
>
> - intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true);
> + intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true,
> + src_w != crtc_w || src_h != crtc_h);
>
> dvsscale = 0;
> if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h)
> --
> 1.8.1.5
>
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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