On 08/01/2013 10:39 AM, Chris Wilson wrote: > Haswell GT3e has the unique feature of supporting Write-Through cacheing > of objects within the eLLC/LLC. The purpose of this is to enable the display > plane to remain coherent whilst objects lie resident in the eLLC/LLC - so > that we, in theory, get the best of both worlds, perfect display and fast > access. > > However, we still need to be careful as the CPU does not see the WT when > accessing the cache. In particular, this means that we need to flush the > cache lines after writing to an object through the CPU, and on > transitioning from a cached state to WT. > I'm planning on adding ioremap_wt, etc sometime soon (for an unrelated reason). Would this be useful here? If so, do you need it for real RAM (i.e. pages that the kernel considers to be direct-mappable RAM) or just for MMIO space? --Andy _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
