Re: [PATCH v2 12/17] drm/i915: Store the watermark latency values in dev_priv

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2013/8/1  <ville.syrjala@xxxxxxxxxxxxxxx>:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Rather than having to read the latency values out every time, just
> store them in dev_priv.
>
> On ILK and IVB there is a difference between some of the latency
> values for different planes, so store the latency values for each
> plane type separately, and apply the necesary fixups during init.
>
> v2: Fix some checkpatch complaints
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 14 ++++++++++
>  drivers/gpu/drm/i915/intel_pm.c | 62 +++++++++++++++++++++++++++++++++++------
>  2 files changed, 67 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fe466bc..bfa5d26 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1214,6 +1214,20 @@ typedef struct drm_i915_private {
>
>         struct i915_suspend_saved_registers regfile;
>
> +       struct {
> +               /*
> +                * Raw watermark latency values:
> +                * in 0.1us units for WM0,
> +                * in 0.5us units for WM1+.
> +                */
> +               /* primary */
> +               uint16_t pri_latency[5];
> +               /* sprite */
> +               uint16_t spr_latency[5];
> +               /* cursor */
> +               uint16_t cur_latency[5];
> +       } wm;
> +
>         /* Old dri1 support infrastructure, beware the dragons ya fools entering
>          * here! */
>         struct i915_dri1_state dri1;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5948f4c..afa7f25 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2367,6 +2367,39 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
>         }
>  }
>
> +static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
> +{
> +       /* ILK sprite LP0 latency is 1300 ns */
> +       if (INTEL_INFO(dev)->gen == 5)
> +               wm[0] = 13;
> +}
> +
> +static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
> +{
> +       /* ILK cursor LP0 latency is 1300 ns */
> +       if (INTEL_INFO(dev)->gen == 5)
> +               wm[0] = 13;
> +
> +       /* WaDoubleCursorLP3Latency:ivb */
> +       if (IS_IVYBRIDGE(dev))
> +               wm[3] *= 2;

I'm looking forward to the future separate patch that will remove this
WA, but I guess it would be better to first finish enabling this code
path on IVB first and only then remove it, so we could easily revert
in case it hurts.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>


> +}
> +
> +static void intel_setup_wm_latency(struct drm_device *dev)
> +{
> +       struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +       intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
> +
> +       memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
> +              sizeof(dev_priv->wm.pri_latency));
> +       memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
> +              sizeof(dev_priv->wm.pri_latency));
> +
> +       intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
> +       intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
> +}
> +
>  static void hsw_compute_wm_parameters(struct drm_device *dev,
>                                       struct hsw_pipe_wm_parameters *params,
>                                       struct hsw_wm_maximums *lp_max_1_2,
> @@ -2612,16 +2645,17 @@ static void haswell_update_wm(struct drm_device *dev)
>         struct hsw_wm_maximums lp_max_1_2, lp_max_5_6;
>         struct hsw_pipe_wm_parameters params[3];
>         struct hsw_wm_values results_1_2, results_5_6, *best_results;
> -       uint16_t wm[5] = {};
>         enum hsw_data_buf_partitioning partitioning;
>
> -       intel_read_wm_latency(dev, wm);
>         hsw_compute_wm_parameters(dev, params, &lp_max_1_2, &lp_max_5_6);
>
> -       hsw_compute_wm_results(dev, params, wm, &lp_max_1_2, &results_1_2);
> +       hsw_compute_wm_results(dev, params,
> +                              dev_priv->wm.pri_latency,
> +                              &lp_max_1_2, &results_1_2);
>         if (lp_max_1_2.pri != lp_max_5_6.pri) {
> -               hsw_compute_wm_results(dev, params, wm, &lp_max_5_6,
> -                                      &results_5_6);
> +               hsw_compute_wm_results(dev, params,
> +                                      dev_priv->wm.pri_latency,
> +                                      &lp_max_5_6, &results_5_6);
>                 best_results = hsw_find_best_result(&results_1_2, &results_5_6);
>         } else {
>                 best_results = &results_1_2;
> @@ -5214,8 +5248,12 @@ void intel_init_pm(struct drm_device *dev)
>
>         /* For FIFO watermark updates */
>         if (HAS_PCH_SPLIT(dev)) {
> +               intel_setup_wm_latency(dev);
> +
>                 if (IS_GEN5(dev)) {
> -                       if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
> +                       if (dev_priv->wm.pri_latency[1] &&
> +                           dev_priv->wm.spr_latency[1] &&
> +                           dev_priv->wm.cur_latency[1])
>                                 dev_priv->display.update_wm = ironlake_update_wm;
>                         else {
>                                 DRM_DEBUG_KMS("Failed to get proper latency. "
> @@ -5224,7 +5262,9 @@ void intel_init_pm(struct drm_device *dev)
>                         }
>                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
>                 } else if (IS_GEN6(dev)) {
> -                       if (SNB_READ_WM0_LATENCY()) {
> +                       if (dev_priv->wm.pri_latency[0] &&
> +                           dev_priv->wm.spr_latency[0] &&
> +                           dev_priv->wm.cur_latency[0]) {
>                                 dev_priv->display.update_wm = sandybridge_update_wm;
>                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
>                         } else {
> @@ -5234,7 +5274,9 @@ void intel_init_pm(struct drm_device *dev)
>                         }
>                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
>                 } else if (IS_IVYBRIDGE(dev)) {
> -                       if (SNB_READ_WM0_LATENCY()) {
> +                       if (dev_priv->wm.pri_latency[0] &&
> +                           dev_priv->wm.spr_latency[0] &&
> +                           dev_priv->wm.cur_latency[0]) {
>                                 dev_priv->display.update_wm = ivybridge_update_wm;
>                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
>                         } else {
> @@ -5244,7 +5286,9 @@ void intel_init_pm(struct drm_device *dev)
>                         }
>                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
>                 } else if (IS_HASWELL(dev)) {
> -                       if (I915_READ64(MCH_SSKPD)) {
> +                       if (dev_priv->wm.pri_latency[0] &&
> +                           dev_priv->wm.spr_latency[0] &&
> +                           dev_priv->wm.cur_latency[0]) {
>                                 dev_priv->display.update_wm = haswell_update_wm;
>                                 dev_priv->display.update_sprite_wm =
>                                         haswell_update_sprite_wm;
> --
> 1.8.1.5
>
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni
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