On Wed, Jul 31, 2013 at 11:31:42AM -0300, Paulo Zanoni wrote: > 2013/7/30 Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>: > > On Mon, Jul 29, 2013 at 05:48:23PM -0300, Paulo Zanoni wrote: > >> From: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> > >> > >> If we're already allowing PC8, just don't use the IRQs, so we won't > >> need to wake from PC8. Waking up from PC8 is a slow thing, so avoid it > >> when we can. > > > > This raises the question of why we where holding the power well wake > > lock if we weren't using IRQs in the first place. > > I can't understand the sentence above. Also notice that the power well > is kinda orthogonal to allowing/disallowing PC8. We need the power > well disabled to allow PC8, but we won't allow PC8 whenever the power > well is disabled. This is the key sentence that is missing that explains why this patch is relevant: > And the GMBUS/DP AUX registers are on the PCH, so > they don't get affected by the state of the power well. That is we can use the gpio pins irrespective of whether either the package state or display power well is enabled. So if the package is asleep, we can use the slightly slower, higher CPU, method to communicate with the display device rather than incur the overhead of powering up the package to monitor IRQs. I have not looked at what is covered by the power wells and by the package cstate - so I am relying on the patch series to teach me and be consistent with the story it tells. (You explain the rationale of the patch in the changelog, and then I can check that the implementation follows suit. And can then also go back and check the rationale against the power management guides, etc.) -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
