Driver always apply panel power off cycle delay before eDP enable.
If eDP display was enabled at pre-os stage, driver would always
trigger modeset to optimize cdclk setting after boot into kernel.
So last_power_on and last_backlight_off value will be updated.
We can check last_power_on and last_backlight_off before insert
panel power cycle delay. If these values are the same, it means eDP
was off until now and driver should bypass this delay to save
some times to speed up eDP power on sequence.
Cc: Shankar Uma <uma.shankar@xxxxxxxxx>
Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx>
Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Signed-off-by: Lee Shawn C <shawn.c.lee@xxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_pps.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 21944f5bf3a8..f3485a4fbfd0 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -509,6 +509,13 @@ static void wait_panel_power_cycle(struct intel_dp *intel_dp)
ktime_t panel_power_on_time;
s64 panel_power_off_duration;
+ /* When last_power_on equal to last_backlight_off, it means driver did not
+ * turn on or off eDP panel so far. So we can bypass power cycle delay to
+ * save some times here.
+ */
+ if (intel_dp->pps.last_power_on == intel_dp->pps.last_backlight_off)
+ return;
+
drm_dbg_kms(&i915->drm, "Wait for panel power cycle\n");
/* take the difference of current time and panel power off time
@@ -1098,9 +1105,11 @@ bool intel_pps_have_panel_power_or_vdd(struct intel_dp *intel_dp)
static void pps_init_timestamps(struct intel_dp *intel_dp)
{
+ unsigned long tmp_jiffies = jiffies;
+
intel_dp->pps.panel_power_off_time = ktime_get_boottime();
- intel_dp->pps.last_power_on = jiffies;
- intel_dp->pps.last_backlight_off = jiffies;
+ intel_dp->pps.last_power_on = tmp_jiffies;
+ intel_dp->pps.last_backlight_off = tmp_jiffies;
}
static void
--
2.17.1
