On Fri, 26 Jul 2013, Egbert Eich <eich@xxxxxxx> wrote:
> For HPD storm detection we now mask out individual interrupt source
> bits. We have already seen a case where HPD interrupt enable bits
> were assigned to the wrong pins. To track these conditions more
> easily add some debugging messages.
The code seems okay, please spellcheck the subject and debug prints! :)
BR,
Jani.
>
> Signed-off-by: Egbert Eich <eich@xxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index ee3e49c..1f3a971 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -919,6 +919,10 @@ static inline void intel_hpd_irq_handler(struct drm_device *dev,
> spin_lock(&dev_priv->irq_lock);
> for (i = 1; i < HPD_NUM_PINS; i++) {
>
> + WARN(((hpd[i] & hotplug_trigger) &&
> + dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED),
> + "Received HPD intterupt although disabled\n");
> +
> if (!(hpd[i] & hotplug_trigger) ||
> dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
> continue;
> @@ -929,6 +933,7 @@ static inline void intel_hpd_irq_handler(struct drm_device *dev,
> + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
> dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
> dev_priv->hpd_stats[i].hpd_cnt = 0;
> + DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
> } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
> dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
> dev_priv->hpd_event_bits &= ~(1 << i);
> @@ -936,6 +941,8 @@ static inline void intel_hpd_irq_handler(struct drm_device *dev,
> storm_detected = true;
> } else {
> dev_priv->hpd_stats[i].hpd_cnt++;
> + DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
> + dev_priv->hpd_stats[i].hpd_cnt);
> }
> }
>
> --
> 1.8.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
