On Mon, Jul 22, 2013 at 12:17:12PM +0100, Damien Lespiau wrote:
> On Mon, Jul 22, 2013 at 08:05:10AM +0200, Daniel Vetter wrote:
> > +static int hdmi_portclock_limit(struct intel_hdmi *hdmi)
> > +{
> > + struct drm_device *dev = intel_hdmi_to_dev(hdmi);
> > +
> > + if (IS_G4X(dev))
> > + return 165000;
> > + else if (IS_HASWELL(dev))
> > + return 340000;
>
> I read 300MHz in the BSpec?
To expand a bit here, HDMI 1.3 and 1.4 have their upper limit defined to
340MHz, but not every piece of hardware is able to achieve that. In our
case the limit seems to be 300MHz for HSW (which apparently is already
enough for some 4k resolutions).
HDMI 1.x and QHD is not that interesting, it can only up to 30Hz. DP
seems the way to go there until HDMI 2.0
--
Damien
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