[PATCH 4/4] drm/i915/display: Add cdclk checks to atomic check

[Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx>]

Checking cdclk conditions during atomic check and preparing
for commit phase so we can have atomic commit as simple
as possible. Add the specific steps to be taken during
cdclk changes, prepare for squashing, crawling and modeset
scenarios.

v2: Add intel_cdclk_modeset() similar to intel_cdclk_squash()
and intel_cdclk_crawl().

Signed-off-by: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 61 ++++++++++++++--------
 1 file changed, 38 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 7bba10635c5e..cb58fc857484 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -38,7 +38,6 @@
 #include "intel_psr.h"
 #include "vlv_sideband.h"
 
-#define ADLP_CDCLK_CRAWL(dev_priv, vco)	(HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0)
 /**
  * DOC: CDCLK / RAWCLK
  *
@@ -1728,27 +1727,10 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 		return;
 	}
 
-	if (!ADLP_CDCLK_CRAWL(dev_priv, vco) && DISPLAY_VER(dev_priv) >= 11) {
-		if (dev_priv->cdclk.hw.vco != 0 &&
-		    dev_priv->cdclk.hw.vco != vco)
-			icl_cdclk_pll_disable(dev_priv);
-
-		if (dev_priv->cdclk.hw.vco != vco)
-			icl_cdclk_pll_enable(dev_priv, vco);
-	} else {
-		if (dev_priv->cdclk.hw.vco != 0 &&
-		    dev_priv->cdclk.hw.vco != vco)
-			bxt_de_pll_disable(dev_priv);
-
-		if (dev_priv->cdclk.hw.vco != vco)
-			bxt_de_pll_enable(dev_priv, vco);
-	}
-
 	waveform = cdclk_squash_waveform(dev_priv, cdclk);
 
-	if ((waveform && has_cdclk_squasher(dev_priv)) || ADLP_CDCLK_CRAWL(dev_priv, vco)) {
-		for (i = 0; i < MAX_CDCLK_ACTIONS; i++) {
-			switch (cdclk_steps[i].action) {
+	for (i = 0; i < MAX_CDCLK_ACTIONS; i++) {
+		switch (cdclk_steps[i].action) {
 			case INTEL_CDCLK_CRAWL:
 				adlp_cdclk_pll_crawl(dev_priv, vco);
 				clock = cdclk;
@@ -1760,15 +1742,28 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 				intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
 				clock = vco / 2;
 				break;
-			case INTEL_CDCLK_NOOP:
 			case INTEL_CDCLK_MODESET:
+				if (DISPLAY_VER(dev_priv) >= 11) {
+					if (dev_priv->cdclk.hw.vco != 0 &&
+					    dev_priv->cdclk.hw.vco != vco)
+						icl_cdclk_pll_disable(dev_priv);
+					if (dev_priv->cdclk.hw.vco != vco)
+						icl_cdclk_pll_enable(dev_priv, vco);
+				} else {
+					if (dev_priv->cdclk.hw.vco != 0 &&
+					    dev_priv->cdclk.hw.vco != vco)
+						bxt_de_pll_disable(dev_priv);
+					if (dev_priv->cdclk.hw.vco != vco)
+						bxt_de_pll_enable(dev_priv, vco);
+				}
+				clock = cdclk;
+				break;
+			case INTEL_CDCLK_NOOP:
 				break;
 			default:
 				break;
 			}
 		}
-	} else
-		clock = cdclk;
 
 	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
 		bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
@@ -2010,6 +2005,24 @@ static bool intel_cdclk_squash(struct drm_i915_private *dev_priv,
 		a->actual.ref == b->actual.ref;
 }
 
+static void intel_cdclk_modeset(struct drm_i915_private *i915,
+				const struct intel_cdclk_config *a,
+				const struct intel_cdclk_config *b)
+{
+	struct intel_cdclk_state *new_cdclk_state;
+	struct cdclk_step *cdclk_transition;
+	struct intel_cdclk_state *cdclk_state =  to_intel_cdclk_state(i915->cdclk.obj.state);
+	struct intel_atomic_state *state = cdclk_state->base.state;
+
+	new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
+	cdclk_transition = new_cdclk_state->steps;
+
+	cdclk_transition[0].action = INTEL_CDCLK_MODESET;
+	cdclk_transition[0].cdclk = b->cdclk;
+	cdclk_transition[1].action = INTEL_CDCLK_NOOP;
+	cdclk_transition[1].cdclk = b->cdclk;
+}
+
 /**
  * intel_cdclk_needs_modeset - Determine if changong between the CDCLK
  *                             configurations requires a modeset on all pipes
@@ -2801,6 +2814,8 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
 			    pipe_name(pipe));
 	} else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual,
 					     &new_cdclk_state->actual)) {
+		intel_cdclk_modeset(dev_priv, &old_cdclk_state->actual,
+				    &new_cdclk_state->actual);
 		/* All pipes must be switched off while we change the cdclk. */
 		ret = intel_modeset_all_pipes(state);
 		if (ret)
-- 
2.25.1