On Fri, Jul 12, 2013 at 02:19:36PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni at intel.com>
>
> The machines that fall in the "is_sdv" case are some very early
> pre-production steppings. This patch may break VGA output after
> suspend/resume on these machines.
>
> Even the documentation for the is_sdv cases was removed from BSpec.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
Was hoping to get through the first 3 before I got too tired, but I
didn't make it. This one is:
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
Will try to finish up some more this weekend.
> ---
> drivers/gpu/drm/i915/intel_display.c | 104 ++++++++++++-----------------------
> 1 file changed, 34 insertions(+), 70 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c79addd..5821ffc 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5170,7 +5170,6 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
> struct drm_mode_config *mode_config = &dev->mode_config;
> struct intel_encoder *encoder;
> bool has_vga = false;
> - bool is_sdv = false;
> u32 tmp;
>
> list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
> @@ -5186,10 +5185,6 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
>
> mutex_lock(&dev_priv->dpio_lock);
>
> - /* XXX: Rip out SDV support once Haswell ships for real. */
> - if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
> - is_sdv = true;
> -
> tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
> tmp &= ~SBI_SSCCTL_DISABLE;
> tmp |= SBI_SSCCTL_PATHALT;
> @@ -5201,36 +5196,27 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
> tmp &= ~SBI_SSCCTL_PATHALT;
> intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
>
> - if (!is_sdv) {
> - tmp = I915_READ(SOUTH_CHICKEN2);
> - tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
> - I915_WRITE(SOUTH_CHICKEN2, tmp);
> + tmp = I915_READ(SOUTH_CHICKEN2);
> + tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
> + I915_WRITE(SOUTH_CHICKEN2, tmp);
>
> - if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
> - FDI_MPHY_IOSFSB_RESET_STATUS, 100))
> - DRM_ERROR("FDI mPHY reset assert timeout\n");
> + if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
> + FDI_MPHY_IOSFSB_RESET_STATUS, 100))
> + DRM_ERROR("FDI mPHY reset assert timeout\n");
>
> - tmp = I915_READ(SOUTH_CHICKEN2);
> - tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
> - I915_WRITE(SOUTH_CHICKEN2, tmp);
> + tmp = I915_READ(SOUTH_CHICKEN2);
> + tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
> + I915_WRITE(SOUTH_CHICKEN2, tmp);
>
> - if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
> - FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
> - 100))
> - DRM_ERROR("FDI mPHY reset de-assert timeout\n");
> - }
> + if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
> + FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
> + DRM_ERROR("FDI mPHY reset de-assert timeout\n");
>
> tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
> tmp &= ~(0xFF << 24);
> tmp |= (0x12 << 24);
> intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
>
> - if (is_sdv) {
> - tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
> - tmp |= 0x7FFF;
> - intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
> - }
> -
> tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
> tmp |= (1 << 11);
> intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
> @@ -5239,24 +5225,6 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
> tmp |= (1 << 11);
> intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
>
> - if (is_sdv) {
> - tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
> - tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
> - intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
> -
> - tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
> - tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
> - intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
> -
> - tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
> - tmp |= (0x3F << 8);
> - intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
> -
> - tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
> - tmp |= (0x3F << 8);
> - intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
> - }
> -
> tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
> tmp |= (1 << 24) | (1 << 21) | (1 << 18);
> intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
> @@ -5265,17 +5233,15 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
> tmp |= (1 << 24) | (1 << 21) | (1 << 18);
> intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
>
> - if (!is_sdv) {
> - tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
> - tmp &= ~(7 << 13);
> - tmp |= (5 << 13);
> - intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
> + tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
> + tmp &= ~(7 << 13);
> + tmp |= (5 << 13);
> + intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
>
> - tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
> - tmp &= ~(7 << 13);
> - tmp |= (5 << 13);
> - intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
> - }
> + tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
> + tmp &= ~(7 << 13);
> + tmp |= (5 << 13);
> + intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
>
> tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
> tmp &= ~0xFF;
> @@ -5297,25 +5263,23 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
> tmp |= (0x1C << 16);
> intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
>
> - if (!is_sdv) {
> - tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
> - tmp |= (1 << 27);
> - intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
> + tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
> + tmp |= (1 << 27);
> + intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
>
> - tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
> - tmp |= (1 << 27);
> - intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
> + tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
> + tmp |= (1 << 27);
> + intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
>
> - tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
> - tmp &= ~(0xF << 28);
> - tmp |= (4 << 28);
> - intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
> + tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
> + tmp &= ~(0xF << 28);
> + tmp |= (4 << 28);
> + intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
>
> - tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
> - tmp &= ~(0xF << 28);
> - tmp |= (4 << 28);
> - intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
> - }
> + tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
> + tmp &= ~(0xF << 28);
> + tmp |= (4 << 28);
> + intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
>
> /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
> tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
> --
> 1.8.1.2
>
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--
Ben Widawsky, Intel Open Source Technology Center
