Customer report abnormal display output while switch eDP off sometimes. In current display disable flow, plane will be off at first. Then turn eDP off and disable HW pipe line. We found the abnormal pixel comes after turn plane off. Clear plane color ctl register when driver disable plane can solve this symptom. Signed-off-by: Lee Shawn C <shawn.c.lee@xxxxxxxxx> Reviewed-by: Uma Shankar <uma.shankar@xxxxxxxxx> --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index caa03324a733..90977cfb7ebb 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -620,6 +620,8 @@ skl_plane_disable_arm(struct intel_plane *plane, intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0); intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0); + if (DISPLAY_VER(dev_priv) >= 10) + intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), 0); } static void @@ -638,6 +640,7 @@ icl_plane_disable_arm(struct intel_plane *plane, intel_psr2_disable_plane_sel_fetch(plane, crtc_state); intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0); intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0); + intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), 0); } static bool -- 2.17.1
