On Fri, 12 Jul 2013 13:03:46 -0700 St?phane Marchesin <marcheu at chromium.org> wrote: > Otherwise the DDI_A_4_LANES bit gets lost and we can't use > 2 lanes > on eDP. This fixes eDP on hsw with > 2 lanes. > > Signed-off-by: St?phane Marchesin <marcheu at chromium.org> > --- > drivers/gpu/drm/i915/intel_ddi.c | 2 +- > drivers/gpu/drm/i915/intel_dp.c | 5 +++-- > 2 files changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index 324211a..5e3f97b 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -1348,7 +1348,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port) > > intel_dig_port->port = port; > intel_dig_port->port_reversal = I915_READ(DDI_BUF_CTL(port)) & > - DDI_BUF_PORT_REVERSAL; > + (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); > intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); > > intel_encoder->type = INTEL_OUTPUT_UNKNOWN; > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index b739712..a1d838c 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -834,10 +834,11 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, > * configuration happens (oddly) in ironlake_pch_enable > */ > > - /* Preserve the BIOS-computed detected bit. This is > + /* Preserve the BIOS-computed detected and 4 lanes bits. This is > * supposed to be read-only. > */ > - intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; > + intel_dp->DP = I915_READ(intel_dp->output_reg) & > + (DP_DETECTED | DDI_A_4_LANES); > > /* Handle DP bits in common between all three register formats */ > intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; Thanks. Wonder if we're clobbering any other "BIOS must set this bit and no one should touch it again" bits elsewhere... Reviewed-by: Jesse Barnes <jbarnes at virtuousgeek.org> -- Jesse Barnes, Intel Open Source Technology Center
