On Thu, Jul 04, 2013 at 11:35:30PM +0200, Daniel Vetter wrote: > The code to handle it is broken - there's simply no code to clear CS > parser errors on gen5+. And behold, for all the other rings we also > don't enable it! > > Leave the handling code itself in place just to be consistent with the > existing mess though. And in case someone feels like fixing it all up. > > This has been errornously enabled in > > commit 12638c57f31952127c734c26315e1348fa1334c2 > Author: Ben Widawsky <ben at bwidawsk.net> > Date: Tue May 28 19:22:31 2013 -0700 > > drm/i915: Enable vebox interrupts > > Cc: Damien Lespiau <damien.lespiau at intel.com> > Cc: Ben Widawsky <ben at bwidawsk.net> > Reviewed-by: Ben Widawsky <ben at bwidawsk.net> > Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch> Ok, I've merged the series up to this patch. Thanks to Ben and Paulo for the review. -Daniel > --- > drivers/gpu/drm/i915/i915_irq.c | 3 +-- > drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +-- > 2 files changed, 2 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 27bf7c1..910912b 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -2812,8 +2812,7 @@ static int ivybridge_irq_postinstall(struct drm_device *dev) > > I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); > if (HAS_VEBOX(dev)) > - pm_irqs |= PM_VEBOX_USER_INTERRUPT | > - PM_VEBOX_CS_ERROR_INTERRUPT; > + pm_irqs |= PM_VEBOX_USER_INTERRUPT; > > /* Our enable/disable rps functions may touch these registers so > * make sure to set a known state for only the non-RPS bits. > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 99d119c..4a0d171 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -2009,8 +2009,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev) > ring->add_request = gen6_add_request; > ring->get_seqno = gen6_ring_get_seqno; > ring->set_seqno = ring_set_seqno; > - ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT | > - PM_VEBOX_CS_ERROR_INTERRUPT; > + ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; > ring->irq_get = hsw_vebox_get_irq; > ring->irq_put = hsw_vebox_put_irq; > ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; > -- > 1.8.1.4 > -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch
