On Mon, Jul 08, 2013 at 02:06:50PM -0300, Paulo Zanoni wrote:
> 2013/7/4 Daniel Vetter <daniel.vetter at ffwll.ch>:
> > Since the addition of VECS we have a slightly different enable
> > sequence for PM interrupts on ivb/hsw vs snb and vlv. Usually that
> > will end up in hard to track down surprises.
> >
> > Hence unifiy things and since we have copies of this code in 3 places
> > now, extract it into its own little helper.
> >
> > v3: Rebase on top of the retained double-GTIIR clearing. Also
> > resurrect the masking/disabling of the gen6+ PM interrupts as spotted
> > by Ben Widaswky.
> >
> > Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 47 ++++++++++++++++++++++-------------------
> > 1 file changed, 25 insertions(+), 22 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index 910912b..f4babaa 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -2581,17 +2581,9 @@ static void ibx_irq_preinstall(struct drm_device *dev)
> > POSTING_READ(SDEIER);
> > }
> >
> > -/* drm_dma.h hooks
> > -*/
> > -static void ironlake_irq_preinstall(struct drm_device *dev)
> > +static void gen5_gt_irq_preinstall(struct drm_device *dev)
> > {
> > - drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
> > -
> > - atomic_set(&dev_priv->irq_received, 0);
> > -
> > - I915_WRITE(HWSTAM, 0xeffe);
> > -
> > - /* XXX hotplug from PCH */
> > + struct drm_i915_private *dev_priv = dev->dev_private;
> >
> > I915_WRITE(DEIMR, 0xffffffff);
> > I915_WRITE(DEIER, 0x0);
>
> So now with your patch, gen5_gt_irq_preinstall is also responsible for
> setting DEIMR+DEIER, but ivybridge_irq_preinstall still sets them, and
> valleyview_irq_preinstall should not touch them. I guess this was an
> accident.
Oops, good catch. I've fixed things up now, will resend the patches after
a bit of testing shortly.
Thanks for your detailed review,
-Daniel
>
>
> > @@ -2602,6 +2594,26 @@ static void ironlake_irq_preinstall(struct drm_device *dev)
> > I915_WRITE(GTIER, 0x0);
> > POSTING_READ(GTIER);
> >
> > + if (INTEL_INFO(dev)->gen >= 6) {
> > + /* and GT */
> > + I915_WRITE(GEN6_PMIMR, 0xffffffff);
> > + I915_WRITE(GEN6_PMIER, 0x0);
> > + POSTING_READ(GEN6_PMIER);
> > + }
> > +}
> > +
> > +/* drm_dma.h hooks
> > +*/
> > +static void ironlake_irq_preinstall(struct drm_device *dev)
> > +{
> > + drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
> > +
> > + atomic_set(&dev_priv->irq_received, 0);
> > +
> > + I915_WRITE(HWSTAM, 0xeffe);
> > +
> > + gen5_gt_irq_preinstall(dev);
> > +
> > ibx_irq_preinstall(dev);
> > }
> >
> > @@ -2619,15 +2631,7 @@ static void ivybridge_irq_preinstall(struct drm_device *dev)
> > I915_WRITE(DEIER, 0x0);
> > POSTING_READ(DEIER);
> >
> > - /* and GT */
> > - I915_WRITE(GTIMR, 0xffffffff);
> > - I915_WRITE(GTIER, 0x0);
> > - POSTING_READ(GTIER);
> > -
> > - /* Power management */
> > - I915_WRITE(GEN6_PMIMR, 0xffffffff);
> > - I915_WRITE(GEN6_PMIER, 0x0);
> > - POSTING_READ(GEN6_PMIER);
> > + gen5_gt_irq_preinstall(dev);
> >
> > ibx_irq_preinstall(dev);
> > }
> > @@ -2648,9 +2652,8 @@ static void valleyview_irq_preinstall(struct drm_device *dev)
> > /* and GT */
> > I915_WRITE(GTIIR, I915_READ(GTIIR));
> > I915_WRITE(GTIIR, I915_READ(GTIIR));
> > - I915_WRITE(GTIMR, 0xffffffff);
> > - I915_WRITE(GTIER, 0x0);
> > - POSTING_READ(GTIER);
> > +
> > + gen5_gt_irq_preinstall(dev);
> >
> > I915_WRITE(DPINVGTT, 0xff);
> >
> > --
> > 1.8.1.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx at lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> Paulo Zanoni
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
