On Sat, Jul 06, 2013 at 04:02:54PM +0100, Chris Wilson wrote: > On Sat, Jul 06, 2013 at 12:52:06PM +0200, Daniel Vetter wrote: > > Section 1.5.4, "DPLL A Control Register" from Bspec about bit 23 > > "FPA0/A1 P2 Clock Divide": > > > > 0 = Divide by 2 > > 1 = Divide by 4. This bit must be set in DVO non-gang mode > > > > So copy the current limits (which should be good for i8xx) and create > > a new set for dvo encoders. > > > > Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch> > Reviewed-by: Chris Wilson <chris at chris-wilson.oc.uk> Both patches merged, thanks for the review. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch
