On Fri, Jul 05, 2013 at 11:57:42AM +0300, ville.syrjala at linux.intel.com wrote: > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > There is a major problem with the watermark registers; they're not > double buffered. So we need to make sure we update them at the correct > time when messing about with planes. The correct time is the beginning > of vblank. > > So when we determine that the watermarks need to updated hand in hand > with the next vblank, we store the pre-computed watermarks under > intel_crtc, and when the vblank happens, we promote the pending > watermarks to active status. > > on HSW when the watermarks for any pipe change, we must merge the > watermarks from all pipes so that we can determine the correct LP1+ > watermark levels. For simplicity we follow the same codepaths for > pre-HSW hardware as well, but there all the LP1+ watermarks will be > disabled when multiple pipes are enabled. Once the watermarks are > merged we check them for validity, disabling any invalid levels. > > Touching the watermark registers causes the hardware to re-evaluate the > watermarks, which expeds some power. So after merging the watermarks > we check which watermark registers actually need to be changed. And > finally we write the watermarks registers in the correct order. Yet you do not justify doing so from interrupt context. A simple way would be to set safe WM (min of current vs next) before the config change, then schedule an update outside of interrupt context after the vblank. I really want an explanation for why doing so in interrupt context is the only sane way. Real power numbers vs complexity please. -Chris -- Chris Wilson, Intel Open Source Technology Centre
