[PATCH] drm/i915: correct intel_dp_get_config() function for DevCPT

[xiong.y.zhang at intel.com (Xiong Zhang)]

On DevCPT, the control register for Transcoder DP Sync Polarity is
TRANS_DP_CTL, not DP_CTL.
Without this patch, Many OOP occur on CPT machine with DP monitor.The OOP
is like: *ERROR* mismatch in adjusted_mode.flags(expected X,found X)

Signed-off-by: Xiong Zhang <xiong.y.zhang at intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c |   57 ++++++++++++++++++++++++++++++++-------
 1 file changed, 47 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8708a0c..16c5803 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1324,20 +1324,57 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
 				struct intel_crtc_config *pipe_config)
 {
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
-	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 	u32 tmp, flags = 0;
+	struct drm_device *dev = encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	enum port port = dp_to_dig_port(intel_dp)->port;
 
-	tmp = I915_READ(intel_dp->output_reg);
+	if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
+		tmp = I915_READ(intel_dp->output_reg);
+		if (tmp & DP_SYNC_HS_HIGH)
+			flags |= DRM_MODE_FLAG_PHSYNC;
+		else
+			flags |= DRM_MODE_FLAG_NHSYNC;
 
-	if (tmp & DP_SYNC_HS_HIGH)
-		flags |= DRM_MODE_FLAG_PHSYNC;
-	else
-		flags |= DRM_MODE_FLAG_NHSYNC;
+		if (tmp & DP_SYNC_VS_HIGH)
+			flags |= DRM_MODE_FLAG_PVSYNC;
+		else
+			flags |= DRM_MODE_FLAG_NVSYNC;
+	} else {
+		u32 trans_sel = 0;
+		int i;
 
-	if (tmp & DP_SYNC_VS_HIGH)
-		flags |= DRM_MODE_FLAG_PVSYNC;
-	else
-		flags |= DRM_MODE_FLAG_NVSYNC;
+		switch (intel_dp->output_reg) {
+		case PCH_DP_B:
+			trans_sel = TRANS_DP_PORT_SEL_B;
+			break;
+		case PCH_DP_C:
+			trans_sel = TRANS_DP_PORT_SEL_C;
+			break;
+		case PCH_DP_D:
+			trans_sel = TRANS_DP_PORT_SEL_D;
+			break;
+		default:
+			break;
+		}
+
+		for_each_pipe(i) {
+			tmp = I915_READ(TRANS_DP_CTL(i));
+			if ((tmp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
+				if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
+					flags |= DRM_MODE_FLAG_PHSYNC;
+				else
+					flags |= DRM_MODE_FLAG_NHSYNC;
+
+				if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
+					flags |= DRM_MODE_FLAG_PVSYNC;
+				else
+					flags |= DRM_MODE_FLAG_NVSYNC;
+
+				break;
+			}
+		}
+	}
 
 	pipe_config->adjusted_mode.flags |= flags;
 }
-- 
1.7.9.5