Reviewing the dotclock computation from the refclk and dividers is a
very useful step in manually checking the register configuration.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_display.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e2e2173..1333a56 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4844,6 +4844,19 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
POSTING_READ(PIPECONF(intel_crtc->pipe));
}
+static u64 compute_dotclock(int refclk, const intel_clock_t *clock)
+{
+ u64 dotclock;
+
+ dotclock = refclk;
+ dotclock *= 5 * (clock->m1 + 2) + clock->m2 + 2;
+ do_div(dotclock, 2+clock->n);
+ do_div(dotclock, clock->p1);
+ do_div(dotclock, clock->p2);
+
+ return dotclock;
+}
+
static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
int x, int y,
struct drm_framebuffer *fb)
@@ -4888,6 +4901,10 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
DRM_ERROR("Couldn't find PLL settings for mode!\n");
return -EINVAL;
}
+ DRM_DEBUG_KMS("refclk=%d, clock=(.m1=%d, .m2=%d, n=%d, .p1=%d, .p2=%d), computed dotclock = %lld\n",
+ refclk, clock.m1, clock.m2, clock.n, clock.p1, clock.p2,
+ compute_dotclock(refclk, &clock));
+
/* Ensure that the cursor is valid for the new mode before changing... */
intel_crtc_update_cursor(crtc, true);
@@ -5736,6 +5753,12 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
DRM_ERROR("Couldn't find PLL settings for mode!\n");
return -EINVAL;
}
+
+ DRM_DEBUG_KMS("refclk=%d, clock=(.m1=%d, .m2=%d, n=%d, .p1=%d, .p2=%d), computed dotclock = %lld\n",
+ ironlake_get_refclk(crtc),
+ clock.m1, clock.m2, clock.n, clock.p1, clock.p2,
+ compute_dotclock(ironlake_get_refclk(crtc), &clock));
+
/* Compat-code for transition, will disappear. */
if (!intel_crtc->config.clock_set) {
intel_crtc->config.dpll.n = clock.n;
--
1.7.10.4
