Signed-off-by: Damien Lespiau <damien.lespiau at intel.com> --- drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index ce14594..009e616 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -171,6 +171,8 @@ gen4_render_ring_flush(struct intel_ring_buffer *ring, * Post-sync nonzero is what triggered this second workaround, so we * can't use that one either. Notify enable is IRQs, which aren't * really our business. That leaves only stall at scoreboard. + * + * WaFlushOpOnCSStall:ivb */ static int intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) @@ -296,6 +298,7 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring, * Workaround: 4th PIPE_CONTROL command (except the ones with only * read-cache invalidate bits set) must have the CS_STALL bit set. We * don't try to be clever and just set it unconditionally. + * WaFlushOpOnCSStall:ivb,hsw,vlv */ flags |= PIPE_CONTROL_CS_STALL; -- 1.8.1.4
