From: Paulo Zanoni <paulo.r.zanoni at intel.com>
These interrupts are specific to Haswell and we don't use them
anywhere inside our code. If we want to allow package C8+ states we
need to make sure we don't have any pending interrupts, so let's
properly initialize the interrupt registers here, so when we allow C8+
states we'll only need to check if these interrupts are still
disabled.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 18 ++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
2 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c482e8a..6706d89 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2539,6 +2539,13 @@ static void ivybridge_irq_preinstall(struct drm_device *dev)
I915_WRITE(GEN6_PMIER, 0x0);
POSTING_READ(GEN6_PMIER);
+ /* Audio */
+ if (IS_HASWELL(dev)) {
+ I915_WRITE(AUDIMR, 0xffffffff);
+ I915_WRITE(AUDIER, 0x0);
+ POSTING_READ(AUDIER);
+ }
+
ibx_irq_preinstall(dev);
}
@@ -2730,6 +2737,11 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
(I915_READ(GEN6_PMIER) & GEN6_PM_RPS_EVENTS) | pm_irqs);
POSTING_READ(GEN6_PMIER);
+ if (IS_HASWELL(dev)) {
+ I915_WRITE(AUDIIR, I915_READ(AUDIIR));
+ POSTING_READ(AUDIIR);
+ }
+
ibx_irq_postinstall(dev);
return 0;
@@ -2837,6 +2849,12 @@ static void ironlake_irq_uninstall(struct drm_device *dev)
I915_WRITE(GTIER, 0x0);
I915_WRITE(GTIIR, I915_READ(GTIIR));
+ if (IS_HASWELL(dev)) {
+ I915_WRITE(AUDIMR, 0xffffffff);
+ I915_WRITE(AUDIER, 0x0);
+ I915_WRITE(AUDIIR, I915_READ(AUDIIR));
+ }
+
if (HAS_PCH_NOP(dev))
return;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 47a9de0..d7f272a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3733,6 +3733,10 @@
#define GTIIR 0x44018
#define GTIER 0x4401c
+#define AUDIMR 0x44084
+#define AUDIIR 0x44088
+#define AUDIER 0x4408c
+
#define ILK_DISPLAY_CHICKEN2 0x42004
/* Required on all Ironlake and Sandybridge according to the B-Spec. */
#define ILK_ELPIN_409_SELECT (1 << 25)
--
1.8.1.2
