2013/6/1 Daniel Vetter <daniel.vetter at ffwll.ch>:
> This prepares a bit for the next big patch, where we switch the
> semantics of the different clocks in the pipe config around.
>
> Since I've broken cpu eDP PLL handling in the first version I've
> figured some refactoring is in order.
>
> Split out on request from Paulo Zanoni.
>
> Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
Possible next steps:
- Uncomplicate those port+gen+pch checks inside intel_dp_mode_set (and
everywhere else inside intel_dp.c).
- Define an enum for 162000, 270000 and 540000 and all the other
possible DP frequencies that might arrive in the future.
> ---
> drivers/gpu/drm/i915/intel_dp.c | 38 ++++++++++++++------------------------
> 1 file changed, 14 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 91a31b3..647cc2b 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -780,24 +780,29 @@ void intel_dp_init_link_config(struct intel_dp *intel_dp)
> }
> }
>
> -static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
> +static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
> {
> - struct drm_device *dev = crtc->dev;
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
> + struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> u32 dpa_ctl;
>
> - DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
> + DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
> + crtc->config.adjusted_mode.clock);
> dpa_ctl = I915_READ(DP_A);
> dpa_ctl &= ~DP_PLL_FREQ_MASK;
>
> - if (clock < 200000) {
> + if (crtc->config.adjusted_mode.clock == 162000) {
> /* For a long time we've carried around a ILK-DevA w/a for the
> * 160MHz clock. If we're really unlucky, it's still required.
> */
> DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
> dpa_ctl |= DP_PLL_FREQ_160MHZ;
> + intel_dp->DP |= DP_PLL_FREQ_160MHZ;
> } else {
> dpa_ctl |= DP_PLL_FREQ_270MHZ;
> + intel_dp->DP |= DP_PLL_FREQ_270MHZ;
> }
>
> I915_WRITE(DP_A, dpa_ctl);
> @@ -814,8 +819,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> enum port port = dp_to_dig_port(intel_dp)->port;
> - struct drm_crtc *crtc = encoder->crtc;
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> + struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
>
> /*
> * There are four kinds of DP registers:
> @@ -845,7 +849,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
>
> if (intel_dp->has_audio) {
> DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
> - pipe_name(intel_crtc->pipe));
> + pipe_name(crtc->pipe));
> intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
> intel_write_eld(encoder, adjusted_mode);
> }
> @@ -864,13 +868,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
> if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
> intel_dp->DP |= DP_ENHANCED_FRAMING;
>
> - intel_dp->DP |= intel_crtc->pipe << 29;
> -
> - /* don't miss out required setting for eDP */
> - if (adjusted_mode->clock < 200000)
> - intel_dp->DP |= DP_PLL_FREQ_160MHZ;
> - else
> - intel_dp->DP |= DP_PLL_FREQ_270MHZ;
> + intel_dp->DP |= crtc->pipe << 29;
> } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
> if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
> intel_dp->DP |= intel_dp->color_range;
> @@ -884,22 +882,14 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
> if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
> intel_dp->DP |= DP_ENHANCED_FRAMING;
>
> - if (intel_crtc->pipe == 1)
> + if (crtc->pipe == 1)
> intel_dp->DP |= DP_PIPEB_SELECT;
> -
> - if (port == PORT_A && !IS_VALLEYVIEW(dev)) {
> - /* don't miss out required setting for eDP */
> - if (adjusted_mode->clock < 200000)
> - intel_dp->DP |= DP_PLL_FREQ_160MHZ;
> - else
> - intel_dp->DP |= DP_PLL_FREQ_270MHZ;
> - }
> } else {
> intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
> }
>
> if (port == PORT_A && !IS_VALLEYVIEW(dev))
> - ironlake_set_pll_edp(crtc, adjusted_mode->clock);
> + ironlake_set_pll_cpu_edp(intel_dp);
> }
>
> #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
> --
> 1.7.11.7
>
--
Paulo Zanoni
