PLANE_CUS_CTL has a restriction of 4096 width even though
PLANE_SIZE and scaler size registers supports max 5120.
Reject 5k on HDR plane for planar formats like NV12
to let the user space know about it.
Without this patch, when 5k content is sent on HDR plane
with NV12 content, FIFO underrun is seen and screen blanks
out. Issue is seen on both TGL and ADL platforms.
Signed-off-by: Vidya Srinivas <vidya.srinivas@xxxxxxxxx>
Signed-off-by: Yashashvi Shantam <shantam.yashashvi@xxxxxxxxx>
---
drivers/gpu/drm/i915/display/skl_scaler.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index 37eabeff8197..e2e52f5dca3b 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -86,6 +86,7 @@ static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
#define ICL_MAX_DST_H 4096
#define SKL_MIN_YUV_420_SRC_W 16
#define SKL_MIN_YUV_420_SRC_H 16
+#define MAX_CUSCTL_W 4096
static int
skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
@@ -221,6 +222,14 @@ int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
bool force_detach = !fb || !plane_state->uapi.visible;
bool need_scaler = false;
+ /* PLANE_CUS_CTL size max 4096 */
+ if (icl_is_hdr_plane(dev_priv, intel_plane->id) &&
+ fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
+ (drm_rect_width(&plane_state->uapi.src) >> 16) > MAX_CUSCTL_W) {
+ DRM_ERROR("HDR chroma upsampler size exceeds limits\n");
+ return -EINVAL;
+ }
+
/* Pre-gen11 and SDR planes always need a scaler for planar formats. */
if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
--
2.33.0
