On Fri, 2013-05-03 at 18:48 +0100, Damien Lespiau wrote:
> We did not mention the workaround name when implementing those. This
> should help us track what we already implement.
>
> Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
On the two patches:
Reviewed-by: Imre Deak <imre.deak at intel.com>
> ---
> drivers/gpu/drm/i915/i915_gem_context.c | 1 +
> drivers/gpu/drm/i915/intel_ddi.c | 2 ++
> drivers/gpu/drm/i915/intel_display.c | 4 ++--
> drivers/gpu/drm/i915/intel_pm.c | 3 +++
> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
> 5 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 9e8c685..c42a411 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -325,6 +325,7 @@ mi_set_context(struct intel_ring_buffer *ring,
> if (ret)
> return ret;
>
> + /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw */
> if (IS_GEN7(ring->dev))
> intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
> else
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 3ff4de6..83e2365 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -174,6 +174,8 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
> * mode set "sequence for CRT port" document:
> * - TP1 to TP2 time with the default value
> * - FDI delay to 90h
> + *
> + * WaFDIAutoLinkSetTimingOverrride:hsw
> */
> I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
> FDI_RX_PWRDN_LANE0_VAL(2) |
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 6504337..7dbec41 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4115,8 +4115,8 @@ static int intel_crtc_compute_config(struct drm_crtc *crtc,
> if (!pipe_config->timings_set)
> drm_mode_set_crtcinfo(adjusted_mode, 0);
>
> - /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
> - * with a hsync front porch of 0.
> + /* Cantiga+ cannot handle modes with a hsync front porch of 0.
> + * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
> */
> if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
> adjusted_mode->hsync_start == adjusted_mode->hdisplay)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5130d26..74b34d4 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4559,6 +4559,7 @@ static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
> FORCEWAKE_ACK_TIMEOUT_MS))
> DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
>
> + /* WaRsForcewakeWaitTC0:snb */
> __gen6_gt_wait_for_thread_c0(dev_priv);
> }
>
> @@ -4590,6 +4591,7 @@ static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
> FORCEWAKE_ACK_TIMEOUT_MS))
> DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
>
> + /* WaRsForcewakeWaitTC0:ivb,hsw */
> __gen6_gt_wait_for_thread_c0(dev_priv);
> }
>
> @@ -4693,6 +4695,7 @@ static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
> FORCEWAKE_ACK_TIMEOUT_MS))
> DRM_ERROR("Timed out waiting for media to ack forcewake request.\n");
>
> + /* WaRsForcewakeWaitTC0:vlv */
> __gen6_gt_wait_for_thread_c0(dev_priv);
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 1d5d613..3d2c236 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -515,6 +515,8 @@ static int init_render_ring(struct intel_ring_buffer *ring)
> /* We need to disable the AsyncFlip performance optimisations in order
> * to use MI_WAIT_FOR_EVENT within the CS. It should already be
> * programmed to '1' on all products.
> + *
> + * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
> */
> if (INTEL_INFO(dev)->gen >= 6)
> I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
