Gen >= 12 onwards MOCS table doesn't have a setting for PTE
so I915_MOCS_PTE is not a valid index and it will have different
MOCS values are based on the platform.
To detect these kinds of misprogramming, all the unspecified and
reserved MOCS indexes are set to WB_L3. TGL/RKL unspecified MOCS
indexes are pointing to L3 UC are kept intact to avoid API break.
This series also contains patches to program BLIT_CCTL and
CMD_CCTL registers to UC.
Since we are quite late to update MOCS table for TGL so added
a new MOCS table for ADL family.
V2:
1. Added CMD_CCTL to GUC regset list so that it can be restored
after engine reset.
2. Checkpatch warning removal.
V3:
1. Changed implementation to have a framework only.
2. Added register type for proper application.
3. moved CMD_CCTL programming to a separate patch.
4. Added L3CC initialization during gt reset so that MOCS indexes are
set before GuC initialization.
5. Removed Renderer check for L3CC verification in selftest.
V4:
1. Moved register programming in Workaorund section as fake workaround.
2. Removed seperate ADL mocs table, new logic is to set unused index as
L3_WB for gen12 platform except TGL/RKL.
V5:
1. Final version reviewed by Matt Roper
2. Removed "drm/i915/selftest: Remove Renderer class check for l3cc table read" form series,
this patch will be taken care of in different series.
Ayaz A Siddiqui (4):
drm/i915/gt: Add support of mocs propagation
drm/i915/gt: Set CMD_CCTL to UC for Gen12 Onward
drm/i915/gt: Set BLIT_CCTL reg to un-cached
drm/i915/gt: Initialize unused MOCS entries with device specific
values
Sreedhar Telukuntla (1):
drm/i915/gt: Initialize L3CC table in mocs init
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +
drivers/gpu/drm/i915/gt/intel_gt_types.h | 4 ++
drivers/gpu/drm/i915/gt/intel_mocs.c | 72 ++++++++++++++-------
drivers/gpu/drm/i915/gt/intel_mocs.h | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 70 +++++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 26 ++++++++
6 files changed, 151 insertions(+), 24 deletions(-)
--
2.26.2
