Hi
2013/5/1 Daniel Vetter <daniel.vetter at ffwll.ch>:
> Every time I read hsw code I get completely confused about this. So
> call it what it is more explicitly.
>
> Also, add an LPT_TRANSCONF for the pch transcoder A and use it in
> lpt-only code, to really unconfuse me.
>
> Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 7 ++++---
> drivers/gpu/drm/i915/i915_ums.c | 8 ++++----
> drivers/gpu/drm/i915/intel_display.c | 30 +++++++++++++++---------------
> 3 files changed, 23 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 95ae5cf..d06a571 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4058,9 +4058,10 @@
> #define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2)
> #define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2)
>
> -#define _TRANSACONF 0xf0008
> -#define _TRANSBCONF 0xf1008
> -#define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF)
> +#define _PCH_TRANSACONF 0xf0008
> +#define _PCH_TRANSBCONF 0xf1008
> +#define PCH_TRANSCONF(plane) _PIPE(plane, _PCH_TRANSACONF, _PCH_TRANSBCONF)
> +#define LPT_TRANSCONF _PCH_TRANSACONF /* lpt has only one transcoder */
Since we're already touching the macros, I need to point that we call
the argument "plane" but use the _PIPE macro, when it's actually a
transcoder :)
Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> #define TRANS_DISABLE (0<<31)
> #define TRANS_ENABLE (1<<31)
> #define TRANS_STATE_MASK (1<<30)
> diff --git a/drivers/gpu/drm/i915/i915_ums.c b/drivers/gpu/drm/i915/i915_ums.c
> index 985a097..75960dd 100644
> --- a/drivers/gpu/drm/i915/i915_ums.c
> +++ b/drivers/gpu/drm/i915/i915_ums.c
> @@ -148,7 +148,7 @@ void i915_save_display_reg(struct drm_device *dev)
> dev_priv->regfile.savePFA_WIN_SZ = I915_READ(_PFA_WIN_SZ);
> dev_priv->regfile.savePFA_WIN_POS = I915_READ(_PFA_WIN_POS);
>
> - dev_priv->regfile.saveTRANSACONF = I915_READ(_TRANSACONF);
> + dev_priv->regfile.saveTRANSACONF = I915_READ(_PCH_TRANSACONF);
> dev_priv->regfile.saveTRANS_HTOTAL_A = I915_READ(_TRANS_HTOTAL_A);
> dev_priv->regfile.saveTRANS_HBLANK_A = I915_READ(_TRANS_HBLANK_A);
> dev_priv->regfile.saveTRANS_HSYNC_A = I915_READ(_TRANS_HSYNC_A);
> @@ -205,7 +205,7 @@ void i915_save_display_reg(struct drm_device *dev)
> dev_priv->regfile.savePFB_WIN_SZ = I915_READ(_PFB_WIN_SZ);
> dev_priv->regfile.savePFB_WIN_POS = I915_READ(_PFB_WIN_POS);
>
> - dev_priv->regfile.saveTRANSBCONF = I915_READ(_TRANSBCONF);
> + dev_priv->regfile.saveTRANSBCONF = I915_READ(_PCH_TRANSBCONF);
> dev_priv->regfile.saveTRANS_HTOTAL_B = I915_READ(_TRANS_HTOTAL_B);
> dev_priv->regfile.saveTRANS_HBLANK_B = I915_READ(_TRANS_HBLANK_B);
> dev_priv->regfile.saveTRANS_HSYNC_B = I915_READ(_TRANS_HSYNC_B);
> @@ -379,7 +379,7 @@ void i915_restore_display_reg(struct drm_device *dev)
> I915_WRITE(_PFA_WIN_SZ, dev_priv->regfile.savePFA_WIN_SZ);
> I915_WRITE(_PFA_WIN_POS, dev_priv->regfile.savePFA_WIN_POS);
>
> - I915_WRITE(_TRANSACONF, dev_priv->regfile.saveTRANSACONF);
> + I915_WRITE(_PCH_TRANSACONF, dev_priv->regfile.saveTRANSACONF);
> I915_WRITE(_TRANS_HTOTAL_A, dev_priv->regfile.saveTRANS_HTOTAL_A);
> I915_WRITE(_TRANS_HBLANK_A, dev_priv->regfile.saveTRANS_HBLANK_A);
> I915_WRITE(_TRANS_HSYNC_A, dev_priv->regfile.saveTRANS_HSYNC_A);
> @@ -448,7 +448,7 @@ void i915_restore_display_reg(struct drm_device *dev)
> I915_WRITE(_PFB_WIN_SZ, dev_priv->regfile.savePFB_WIN_SZ);
> I915_WRITE(_PFB_WIN_POS, dev_priv->regfile.savePFB_WIN_POS);
>
> - I915_WRITE(_TRANSBCONF, dev_priv->regfile.saveTRANSBCONF);
> + I915_WRITE(_PCH_TRANSBCONF, dev_priv->regfile.saveTRANSBCONF);
> I915_WRITE(_TRANS_HTOTAL_B, dev_priv->regfile.saveTRANS_HTOTAL_B);
> I915_WRITE(_TRANS_HBLANK_B, dev_priv->regfile.saveTRANS_HBLANK_B);
> I915_WRITE(_TRANS_HSYNC_B, dev_priv->regfile.saveTRANS_HSYNC_B);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2939524..9ee2f9e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1206,14 +1206,14 @@ static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
> WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
> }
>
> -static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
> - enum pipe pipe)
> +static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
> + enum pipe pipe)
> {
> int reg;
> u32 val;
> bool enabled;
>
> - reg = TRANSCONF(pipe);
> + reg = PCH_TRANSCONF(pipe);
> val = I915_READ(reg);
> enabled = !!(val & TRANS_ENABLE);
> WARN(enabled,
> @@ -1565,7 +1565,7 @@ static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
> DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
>
> /* Make sure transcoder isn't still depending on us */
> - assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
> + assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
>
> reg = pll->pll_reg;
> val = I915_READ(reg);
> @@ -1605,7 +1605,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
> I915_WRITE(reg, val);
> }
>
> - reg = TRANSCONF(pipe);
> + reg = PCH_TRANSCONF(pipe);
> val = I915_READ(reg);
> pipeconf_val = I915_READ(PIPECONF(pipe));
>
> @@ -1659,8 +1659,8 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
> else
> val |= TRANS_PROGRESSIVE;
>
> - I915_WRITE(TRANSCONF(TRANSCODER_A), val);
> - if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
> + I915_WRITE(LPT_TRANSCONF, val);
> + if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
> DRM_ERROR("Failed to enable PCH transcoder\n");
> }
>
> @@ -1677,7 +1677,7 @@ static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
> /* Ports must be off as well */
> assert_pch_ports_disabled(dev_priv, pipe);
>
> - reg = TRANSCONF(pipe);
> + reg = PCH_TRANSCONF(pipe);
> val = I915_READ(reg);
> val &= ~TRANS_ENABLE;
> I915_WRITE(reg, val);
> @@ -1698,11 +1698,11 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
> {
> u32 val;
>
> - val = I915_READ(_TRANSACONF);
> + val = I915_READ(LPT_TRANSCONF);
> val &= ~TRANS_ENABLE;
> - I915_WRITE(_TRANSACONF, val);
> + I915_WRITE(LPT_TRANSCONF, val);
> /* wait for PCH transcoder off, transcoder state */
> - if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
> + if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
> DRM_ERROR("Failed to disable PCH transcoder\n");
>
> /* Workaround: clear timing override bit. */
> @@ -3011,7 +3011,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
> int pipe = intel_crtc->pipe;
> u32 reg, temp;
>
> - assert_transcoder_disabled(dev_priv, pipe);
> + assert_pch_transcoder_disabled(dev_priv, pipe);
>
> /* Write the TU size bits before fdi link training, so that error
> * detection works. */
> @@ -3115,7 +3115,7 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
>
> - assert_transcoder_disabled(dev_priv, TRANSCODER_A);
> + assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
>
> lpt_program_iclkip(crtc);
>
> @@ -5899,7 +5899,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
> if (!(tmp & PIPECONF_ENABLE))
> return false;
>
> - if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
> + if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
> pipe_config->has_pch_encoder = true;
>
> tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
> @@ -6048,7 +6048,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
> */
> tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
> if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
> - I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE) {
> + I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
> pipe_config->has_pch_encoder = true;
>
> tmp = I915_READ(FDI_RX_CTL(PIPE_A));
> --
> 1.8.1.4
>
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> Intel-gfx at lists.freedesktop.org
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--
Paulo Zanoni
