Update the way we handle shadowed registers (i.e., registers that we can write to without grabbing forcewake first) to support register ranges rather than just single registers, and add some missing registers for gen11, gen12, and Xe_HP. While we're working in this area of the code, let's also adjust the description of the GT domain in error messages (referring to it as 'blitter' just confuses people) and eliminate some unnecessary duplication of forcewake read functions. Matt Roper (6): drm/i915: correct name of GT forcewake domain in error messages drm/i915: Re-use gen11 forcewake read functions on gen12 drm/i915: Make shadow tables range-based drm/i915/gen11: Update shadowed register table drm/i915/gen12: Update shadowed register table drm/i915/xehp: Xe_HP shadowed registers are a strict superset of gen12 drivers/gpu/drm/i915/gt/intel_workarounds.c | 13 +- drivers/gpu/drm/i915/intel_uncore.c | 185 ++++++++---------- drivers/gpu/drm/i915/intel_uncore.h | 6 + drivers/gpu/drm/i915/selftests/intel_uncore.c | 33 ++-- 4 files changed, 111 insertions(+), 126 deletions(-) -- 2.25.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
