On Wed, Apr 24, 2013 at 02:52:52PM +0100, Chris Wilson wrote: > On Wed, Apr 24, 2013 at 03:46:04PM +0200, Daniel Vetter wrote: > > If we ever leak a non-DP compliant port width through here, we have a > > pretty serious issue. So just rip out all these WARNs - if we need > > them it's probably better to have them at a central place where we > > compute the dp lane count. > > > > Also use the new DDI width macro for FDI mode. > > > > Cc: Paulo Zanoni <paulo.r.zanoni at intel.com> > > Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch> > > Nice. Do we have the central warn though? > Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk> Well the current dp lane count compute uses shifts, so is pretty much guaranteed to end up with a power of two value. I've figured smashing WARN right below that looks silly. Compared to eg the pipe bpc stuff we also don't have different limits on different platforms, so either it's broken everywhere or nowhere. The only case that's different is fdi mode on haswell, but the old code didn't have a paranoid check either. So I've figured I'll let it be. Especially since the current code lets invalid configs slip through (that needs my fdi patches to work properly) ... All in all I'm voting for the "wait for godzilla to smash things" approach here ;-) -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch
