On Thu, Jul 08, 2021 at 02:18:22PM -0700, José Roberto de Souza wrote: > Same bit was required for Wa_14012131227 in DG1 now it is also This is a DG1-specific number; the general lineage number given here and in the comment should be 22011054531 (and this lineage number does apply to TGL, RKL, ADL-S, ADL-P, and DG1 too). > required as Wa_1508744258 to TGL, RKL, DG1, ADL-S and ADL-P. Technically it's still working its way through the process to become official on RKL, but given that it's already an official workaround under the other number, I think it's safe to assume this one will become official too. > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@xxxxxxxxx> > Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx> Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index e5e3f820074a9..c346229e2be00 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -670,6 +670,13 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, > FF_MODE2_GS_TIMER_MASK, > FF_MODE2_GS_TIMER_224, > 0); > + > + /* > + * Wa_14012131227:dg1 > + * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p > + */ > + wa_masked_en(wal, GEN7_COMMON_SLICE_CHICKEN1, > + GEN9_RHWO_OPTIMIZATION_DISABLE); > } > > static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, > -- > 2.32.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
