On Fri, Apr 19, 2013 at 5:14 AM, Daniel Vetter <daniel.vetter at ffwll.ch> wrote:
> g4x dplls and ilk+ pch plls have a separate field for the reduced p1
> setting, so this restriction does not apply. Only older platforms have
> the restriction that the p1 divisors must match.
>
> This unnecessary restriction has been introduced in
>
> commit cec2f356d59d9e070413e5966a3c5a1af136d948
> Author: Sean Paul <seanpaul at chromium.org>
> Date: Tue Jan 10 15:09:36 2012 -0800
>
> drm/i915: Only look for matching clocks for LVDS downcloc
>
> Note that with lvds the p2 divisors _always_ match for LVDS, and we
> don't support auto-downclocking anywhere else. On eDP downclocking
> works with separate data m/n settings, using the same link clock.
>
> Cc: Sean Paul <seanpaul at chromium.org>
> Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Reviewed-by: Sean Paul <seanpaul at chromium.org>
> ---
> drivers/gpu/drm/i915/intel_display.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2a82bd8..9a69d83 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -697,9 +697,6 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
> if (!intel_PLL_is_valid(dev, limit,
> &clock))
> continue;
> - if (match_clock &&
> - clock.p != match_clock->p)
> - continue;
>
> this_err = abs(clock.dot - target);
> if (this_err < err_most) {
> --
> 1.7.11.7
>
