On Fri, 2013-04-12 at 17:57 -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni at intel.com>
>
> This is bad news and shouldn't be happening.
>
> V2: Rebase.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
Looks ok:
Reviewed-by: Imre Deak <imre.deak at intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 13 +++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> 2 files changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 9aff6ed..8b2461b 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -939,6 +939,9 @@ static void ivb_err_int_handler(struct drm_device *dev)
> struct drm_i915_private *dev_priv = dev->dev_private;
> u32 err_int = I915_READ(GEN7_ERR_INT);
>
> + if (err_int & ERR_INT_POISON)
> + DRM_ERROR("Poison interrupt\n");
> +
> if (err_int & ERR_INT_FIFO_UNDERRUN_A)
> if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
> DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
> @@ -959,6 +962,9 @@ static void cpt_serr_int_handler(struct drm_device *dev)
> struct drm_i915_private *dev_priv = dev->dev_private;
> u32 serr_int = I915_READ(SERR_INT);
>
> + if (serr_int & SERR_INT_POISON)
> + DRM_ERROR("PCH poison interrupt\n");
> +
> if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
> if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
> false))
> @@ -1172,6 +1178,9 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
> if (de_iir & DE_PIPEB_VBLANK)
> drm_handle_vblank(dev, 1);
>
> + if (de_iir & DE_POISON)
> + DRM_ERROR("Poison interrupt\n");
> +
> if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
> if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
> DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
> @@ -2403,7 +2412,7 @@ static void ibx_irq_postinstall(struct drm_device *dev)
>
> if (HAS_PCH_IBX(dev)) {
> mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
> - SDE_TRANSA_FIFO_UNDER;
> + SDE_TRANSA_FIFO_UNDER | SDE_POISON;
> } else {
> mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
>
> @@ -2424,7 +2433,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
> u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
> DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
> DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
> - DE_PIPEA_FIFO_UNDERRUN;
> + DE_PIPEA_FIFO_UNDERRUN | DE_POISON;
> u32 render_irqs;
>
> dev_priv->irq_mask = ~display_mask;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 932b4a0..68a27e1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -529,6 +529,7 @@
>
> #define ERROR_GEN6 0x040a0
> #define GEN7_ERR_INT 0x44040
> +#define ERR_INT_POISON (1<<31)
> #define ERR_INT_MMIO_UNCLAIMED (1<<13)
> #define ERR_INT_FIFO_UNDERRUN_C (1<<6)
> #define ERR_INT_FIFO_UNDERRUN_B (1<<3)
> @@ -3693,6 +3694,7 @@
> #define SDEIER 0xc400c
>
> #define SERR_INT 0xc4040
> +#define SERR_INT_POISON (1<<31)
> #define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6)
> #define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3)
> #define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0)
