On Wed, Apr 17, 2013 at 06:25:29PM +0100, Chris Wilson wrote: > On Wed, Apr 17, 2013 at 08:11:58PM +0300, ville.syrjala at linux.intel.com wrote: > > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > The docs say that the trickle feed disable bit is present (for primary > > planes only, not video sprites) on BLC and CTG, and that it must be set > > for ELK. Just set it for all g4x chipset. > > > > Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > I'm stunned that we did all the post-pch chipsets but missed g4x. > Perhaps we should also do it during init_clock_gating() as we do for > other generations? Actually we do it in both ironlake_update_plane() and init_clock_gating() for gen5+. I guess someone wanted to make sure the bit sticks ;) I'm thinking I'd rather kill the init_clock_gating() parts since that would keep the whole plane setup in one place. -- Ville Syrj?l? Intel OTC
