On Wed, Apr 10, 2013 at 06:23:25PM +0300, Imre Deak wrote:
> On Mon, 2013-04-08 at 15:48 -0300, Paulo Zanoni wrote:
> > From: Paulo Zanoni <paulo.r.zanoni at intel.com>
> >
> > Bits 30 and 24:0 are PBC, so don't zero them. Some of the other bits
> > are being zeroed, but I couldn't find a reason for this, so leave them
> > as they are for now to avoid regressions.
> >
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++--
> > drivers/gpu/drm/i915/intel_pm.c | 7 ++++++-
> > 2 files changed, 12 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 759b1b8..f4d6673 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3949,8 +3949,12 @@
> > #define _TRANSA_CHICKEN2 0xf0064
> > #define _TRANSB_CHICKEN2 0xf1064
> > #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
> > -#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
> > -#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
> > +#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
> > +#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
> > +#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27)
> > +#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26)
> > +#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25)
> > +#define TRANS_CHICKEN2_PBC (1<<30 | 0x1ffffff)
>
> The above _PBC value seems to be redundant. In any case on both patches:
> Reviewed-by: Imre Deak <imre.deak at intel.com>
Redundant #define deleted and both patches merged, thanks.
-Daniel
>
> >
> > #define SOUTH_CHICKEN1 0xc2000
> > #define FDIA_PHASE_SYNC_SHIFT_OVR 19
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index ce3d892..e4ead41 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3589,9 +3589,14 @@ static void cpt_init_clock_gating(struct drm_device *dev)
> > * downward, on (only) LVDS of some HP laptops with IVY.
> > */
> > for_each_pipe(pipe) {
> > - val = TRANS_CHICKEN2_TIMING_OVERRIDE;
> > + val = I915_READ(TRANS_CHICKEN2(pipe));
> > + val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
> > + val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
> > if (dev_priv->fdi_rx_polarity_inverted)
> > val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
> > + val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
> > + val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
> > + val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
> > I915_WRITE(TRANS_CHICKEN2(pipe), val);
> > }
> > /* WADP0ClockGatingDisable */
>
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
