According to SNB GT PM Programming Guide Turbo, page 8, GEN6_RPNSWREQ (A008)
bit [31] must be set as 0 meaning Turbo Disable.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5e91fbb..fc4f542f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4220,7 +4220,7 @@
#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
#define GEN6_RPNSWREQ 0xA008
-#define GEN6_TURBO_DISABLE (1<<31)
+#define GEN6_TURBO_DISABLE (0<<31)
#define GEN6_FREQUENCY(x) ((x)<<25)
#define HSW_FREQUENCY(x) ((x)<<24)
#define GEN6_OFFSET(x) ((x)<<19)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 27f94cd..e3ba13d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2465,6 +2465,7 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
HSW_FREQUENCY(val));
else
I915_WRITE(GEN6_RPNSWREQ,
+ GEN6_TURBO_DISABLE |
GEN6_FREQUENCY(val) |
GEN6_OFFSET(0) |
GEN6_AGGRESSIVE_TURBO);
@@ -2612,6 +2613,7 @@ static void gen6_enable_rps(struct drm_device *dev)
HSW_FREQUENCY(12));
} else {
I915_WRITE(GEN6_RPNSWREQ,
+ GEN6_TURBO_DISABLE |
GEN6_FREQUENCY(10) |
GEN6_OFFSET(0) |
GEN6_AGGRESSIVE_TURBO);
--
1.8.1.4
