On Tue, Apr 9, 2013 at 5:35 AM, Ville Syrj?l? <ville.syrjala at linux.intel.com
> wrote:
> On Mon, Apr 08, 2013 at 06:49:42PM -0300, Rodrigo Vivi wrote:
> > This patch introduce Frame Buffer Compression (FBC) support for HSW.
> > It adds a new function haswell_enable_fbc to avoid getting
> > ironlake_enable_fbc messed with many IS_HASWELL checks.
> >
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.c | 1 +
> > drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
> > drivers/gpu/drm/i915/intel_pm.c | 44
> ++++++++++++++++++++++++++++++++++++++++-
> > 3 files changed, 50 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> b/drivers/gpu/drm/i915/i915_drv.c
> > index 0cfc778..88fd6fb 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -291,6 +291,7 @@ static const struct intel_device_info
> intel_haswell_m_info = {
> > GEN7_FEATURES,
> > .is_haswell = 1,
> > .is_mobile = 1,
> > + .has_fbc = 1,
> > };
> >
> > static const struct pci_device_id pciidlist[] = { /* aka */
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> > index 5e91fbb..cb8e213 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -849,6 +849,12 @@
> > #define SNB_CPU_FENCE_ENABLE (1<<29)
> > #define DPFC_CPU_FENCE_OFFSET 0x100104
> >
> > +/* Framebuffer compression for Haswell */
> > +#define HSW_FBC_RT_BASE 0x7020
> > +#define HSW_FBC_RT_BASE_ADDR_SHIFT 12
> > +
> > +#define HSW_DPFC_CTL_FENCE_EN (1<<28)
> > +#define HSW_DPFC_CTL_DISABLE_SLB_INIT (1<<15)
> >
> > /*
> > * GPIO regs
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> > index 27f94cd..94e1c3a 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -253,6 +253,43 @@ static bool ironlake_fbc_enabled(struct drm_device
> *dev)
> > return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
> > }
> >
> > +static void haswell_enable_fbc(struct drm_crtc *crtc, unsigned long
> interval)
> > +{
> > + struct drm_device *dev = crtc->dev;
> > + struct drm_i915_private *dev_priv = dev->dev_private;
> > + struct drm_framebuffer *fb = crtc->fb;
> > + struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> > + struct drm_i915_gem_object *obj = intel_fb->obj;
> > + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > + int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
> DPFC_CTL_PLANEB;
> > + unsigned long stall_watermark = 200;
> > + u32 dpfc_ctl;
> > +
> > + dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
> > + dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
>
> Accroding to BSpec FBC is always tied to plane A. Bit 30 is MBZ.
>
Yeah, you are right. I'm going to add a verification at begining like:
if (intel_crtc->plane != PLANE_A) {
dev_priv->no_fbc_reason = FBC_BAD_PLANE;
return;
}
> Maybe fix up plane C FBC support for IVB while you're poking at the
> general direction?
>
Actually I wasn't trying general directions since I splited it out. It was
just bad copy and paste actually.
>
> > + dpfc_ctl |= (HSW_DPFC_CTL_FENCE_EN | obj->fence_reg);
>
> The CPU fence field must be written with 0. SNB/IVB could do with the
> same fix.
>
Where did you get this restriction for HSW? Should we write 0 or not touch
by removing lis line?
Thanks for all your comments!
>
> > + dpfc_ctl |= HSW_DPFC_CTL_DISABLE_SLB_INIT;
> > + I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
> > + (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
> > + (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
> > + I915_WRITE(HSW_FBC_RT_BASE,
> > + obj->gtt_offset << HSW_FBC_RT_BASE_ADDR_SHIFT |
> > + ILK_FBC_RT_VALID);
> > + /* enable it... */
> > + I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
> > +
> > + if (obj->fence_reg != I915_FENCE_REG_NONE) {
> > + I915_WRITE(SNB_DPFC_CTL_SA,
> > + SNB_CPU_FENCE_ENABLE | obj->fence_reg);
> > + I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
> > + } else
> > + I915_WRITE(SNB_DPFC_CTL_SA, ~SNB_CPU_FENCE_ENABLE);
> > +
> > + sandybridge_blit_fbc_update(dev);
> > +
> > + DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
> > +}
> > +
> > bool intel_fbc_enabled(struct drm_device *dev)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -4158,7 +4195,12 @@ void intel_init_pm(struct drm_device *dev)
> > if (I915_HAS_FBC(dev)) {
> > if (HAS_PCH_SPLIT(dev)) {
> > dev_priv->display.fbc_enabled =
> ironlake_fbc_enabled;
> > - dev_priv->display.enable_fbc = ironlake_enable_fbc;
> > + if (IS_HASWELL(dev))
> > + dev_priv->display.enable_fbc =
> > + haswell_enable_fbc;
> > + else
> > + dev_priv->display.enable_fbc =
> > + ironlake_enable_fbc;
> > dev_priv->display.disable_fbc =
> ironlake_disable_fbc;
> > } else if (IS_GM45(dev)) {
> > dev_priv->display.fbc_enabled = g4x_fbc_enabled;
> > --
> > 1.8.1.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx at lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrj?l?
> Intel OTC
>
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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