On Fri, Apr 05, 2013 at 04:52:28PM -0300, Paulo Zanoni wrote: > Hi > > 2013/4/4 Daniel Vetter <daniel.vetter at ffwll.ch>: > > commit de13a2e3f88a4da8e85063b6de37096795079e41 > > Author: Paulo Zanoni <paulo.r.zanoni at intel.com> > > Date: Thu Sep 20 18:36:05 2012 -0300 > > > > drm/i915: extract compute_dpll from ironlake_crtc_mode_set > > > > missed the subtle adjustment of the FP1 register. Fix this up by > > passing a pointer around instead of the value. > > We could also move the whole chunk that sets "factor" and "FP_CB_TUNE" > back to ironlake_crtc_mode_set or even to a brand new > ironlake_calculate_fp(intel_crtc, clock, has_reduced_clock, > reduced_clock, &fp, &fp2). Maybe as a follow-up patch since this > version is way much easier for -stable. > > Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com> All patches merged, thanks for the review. I didn't add a cc: stable to this one, since no one has reported a regression yet. We can easily backport if that changes. I agree with your refactor idea, but until all the clock handling has settled a bit (due to the massive pipe config reorganisation) I think we should hold and not waste too much time with beauty-ops ;-) Cheers, Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch
