[PATCH 2/8] drm/i915: move dp_m_n computation to dp_encoder->compute_config

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On Thu, 28 Mar 2013 10:41:57 +0100
Daniel Vetter <daniel.vetter at ffwll.ch> wrote:

> We need a flag to designate dp encoders and the dp link m_n parameters
> in the pipe config for that. And now that the pipe bpp computations
> have been moved up and stored in the pipe config, too, we can do this
> without losing our sanity.
> 
> v2: Rebased on top of Takashi Iwai's fix to (again) fix the target
> clock handling for eDP. Luckily the new code is sane enough and just
> does the right thing!
> 
> Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 30 +++++++++---------
>  drivers/gpu/drm/i915/intel_dp.c      | 59 ++++++------------------------------
>  drivers/gpu/drm/i915/intel_drv.h     |  3 --
>  3 files changed, 25 insertions(+), 67 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a53a02c..dfa8919 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4182,6 +4182,14 @@ static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
>  	}
>  }
>  
> +static void intel_dp_set_m_n(struct intel_crtc *crtc)
> +{
> +	if (crtc->config.has_pch_encoder)
> +		intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
> +	else
> +		intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
> +}
> +
>  static void vlv_update_pll(struct drm_crtc *crtc,
>  			   intel_clock_t *clock, intel_clock_t *reduced_clock,
>  			   int num_connectors)
> @@ -4189,9 +4197,6 @@ static void vlv_update_pll(struct drm_crtc *crtc,
>  	struct drm_device *dev = crtc->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	struct drm_display_mode *adjusted_mode =
> -		&intel_crtc->config.adjusted_mode;
> -	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
>  	int pipe = intel_crtc->pipe;
>  	u32 dpll, mdiv, pdiv;
>  	u32 bestn, bestm1, bestm2, bestp1, bestp2;
> @@ -4247,8 +4252,8 @@ static void vlv_update_pll(struct drm_crtc *crtc,
>  
>  	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
>  
> -	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
> -		intel_dp_set_m_n(crtc, mode, adjusted_mode);
> +	if (intel_crtc->config.has_dp_encoder)
> +		intel_dp_set_m_n(intel_crtc);
>  
>  	I915_WRITE(DPLL(pipe), dpll);
>  
> @@ -4294,9 +4299,6 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
>  	struct drm_device *dev = crtc->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	struct drm_display_mode *adjusted_mode =
> -		&intel_crtc->config.adjusted_mode;
> -	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
>  	struct intel_encoder *encoder;
>  	int pipe = intel_crtc->pipe;
>  	u32 dpll;
> @@ -4371,8 +4373,8 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
>  		if (encoder->pre_pll_enable)
>  			encoder->pre_pll_enable(encoder);
>  
> -	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
> -		intel_dp_set_m_n(crtc, mode, adjusted_mode);
> +	if (intel_crtc->config.has_dp_encoder)
> +		intel_dp_set_m_n(intel_crtc);
>  
>  	I915_WRITE(DPLL(pipe), dpll);
>  
> @@ -5588,8 +5590,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
>  	} else
>  		intel_put_pch_pll(intel_crtc);
>  
> -	if (is_dp)
> -		intel_dp_set_m_n(crtc, mode, adjusted_mode);
> +	if (intel_crtc->config.has_dp_encoder)
> +		intel_dp_set_m_n(intel_crtc);
>  
>  	for_each_encoder_on_crtc(dev, crtc, encoder)
>  		if (encoder->pre_pll_enable)
> @@ -5738,8 +5740,8 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
>  	DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
>  	drm_mode_debug_printmodeline(mode);
>  
> -	if (is_dp)
> -		intel_dp_set_m_n(crtc, mode, adjusted_mode);
> +	if (intel_crtc->config.has_dp_encoder)
> +		intel_dp_set_m_n(intel_crtc);
>  
>  	intel_crtc->lowfreq_avail = false;
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 6b8a279..ef680d5 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -193,6 +193,8 @@ intel_dp_mode_valid(struct drm_connector *connector,
>  
>  		if (mode->vdisplay > fixed_mode->vdisplay)
>  			return MODE_PANEL;
> +
> +		target_clock = fixed_mode->clock;
>  	}
>  
>  	max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
> @@ -688,6 +690,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp))
>  		pipe_config->has_pch_encoder = true;
>  
> +	pipe_config->has_dp_encoder = true;
> +
>  	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
>  		intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
>  				       adjusted_mode);
> @@ -707,7 +711,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  
>  	/* Walk through all bpp values. Luckily they're all nicely spaced with 2
>  	 * bpc in between. */
> -	bpp = 8*3;
> +	bpp = min_t(int, 8*3, pipe_config->pipe_bpp);
>  	if (is_edp(intel_dp) && dev_priv->edp.bpp)
>  		bpp = min_t(int, bpp, dev_priv->edp.bpp);
>  
> @@ -756,56 +760,11 @@ found:
>  	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
>  		      mode_rate, link_avail);
>  
> -	return true;
> -}
> -
> -void
> -intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
> -		 struct drm_display_mode *adjusted_mode)
> -{
> -	struct drm_device *dev = crtc->dev;
> -	struct intel_encoder *intel_encoder;
> -	struct intel_dp *intel_dp;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	int lane_count = 4;
> -	struct intel_link_m_n m_n;
> -	int target_clock;
> -
> -	/*
> -	 * Find the lane count in the intel_encoder private
> -	 */
> -	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
> -		intel_dp = enc_to_intel_dp(&intel_encoder->base);
> -
> -		if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
> -		    intel_encoder->type == INTEL_OUTPUT_EDP)
> -		{
> -			lane_count = intel_dp->lane_count;
> -			break;
> -		}
> -	}
> -
> -	target_clock = mode->clock;
> -	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
> -		if (intel_encoder->type == INTEL_OUTPUT_EDP) {
> -			target_clock = intel_edp_target_clock(intel_encoder,
> -							      mode);
> -			break;
> -		}
> -	}
> -
> -	/*
> -	 * Compute the GMCH and Link ratios. The '3' here is
> -	 * the number of bytes_per_pixel post-LUT, which we always
> -	 * set up for 8-bits of R/G/B, or 3 bytes total.
> -	 */
> -	intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane_count,
> -			       target_clock, adjusted_mode->clock, &m_n);
> +	intel_link_compute_m_n(bpp, lane_count,
> +			       target_clock, adjusted_mode->clock,
> +			       &pipe_config->dp_m_n);
>  
> -	if (intel_crtc->config.has_pch_encoder)
> -		intel_pch_transcoder_set_m_n(intel_crtc, &m_n);
> -	else
> -		intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
> +	return true;
>  }
>  
>  void intel_dp_init_link_config(struct intel_dp *intel_dp)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 3a9b7be..41fabcb 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -473,9 +473,6 @@ extern void intel_dp_init(struct drm_device *dev, int output_reg,
>  			  enum port port);
>  extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>  				    struct intel_connector *intel_connector);
> -void
> -intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
> -		 struct drm_display_mode *adjusted_mode);
>  extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
>  extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
>  extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);

Looks good.

with the field from 1/8 moved to this patch:
Reviewed-by: Jesse Barnes <jbarnes at virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center


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