On Fri, Feb 22, 2013 at 05:05:30PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni at intel.com>
>
> This is bad news and shouldn't be happening.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
No bikesheds here and I like this. So when you resend the underrun
reporting patch, please also resend this one here, thanks.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_irq.c | 14 ++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> 2 files changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index d0f9c47..98a57ed 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -875,6 +875,9 @@ static void err_int_handler(struct drm_device *dev)
> struct drm_i915_private *dev_priv = dev->dev_private;
> u32 err_int = I915_READ(GEN7_ERR_INT);
>
> + if (err_int & ERR_INT_POISON)
> + DRM_ERROR("Poison interrupt\n");
> +
> if (err_int & ERR_INT_FIFO_UNDERRUN_A)
> if (intel_report_cpu_fifo_underrun(dev, PIPE_A, false))
> DRM_ERROR("Pipe A FIFO underrun\n");
> @@ -895,6 +898,9 @@ static void serr_int_handler(struct drm_device *dev)
> struct drm_i915_private *dev_priv = dev->dev_private;
> u32 serr_int = I915_READ(SERR_INT);
>
> + if (serr_int & SERR_INT_POISON)
> + DRM_ERROR("PCH poison interrupt\n");
> +
> if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
> if (intel_report_pch_fifo_underrun(dev, TRANSCODER_A, false))
> DRM_ERROR("PCH transcoder A FIFO underrun\n");
> @@ -1101,6 +1107,9 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
> if (de_iir & DE_PIPEB_VBLANK)
> drm_handle_vblank(dev, 1);
>
> + if (de_iir & DE_POISON)
> + DRM_ERROR("Poison interrupt\n");
> +
> if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
> if (intel_report_cpu_fifo_underrun(dev, PIPE_A, false))
> DRM_ERROR("Pipe A FIFO underrun\n");
> @@ -2247,7 +2256,8 @@ static void ibx_irq_postinstall(struct drm_device *dev)
> SDE_GMBUS |
> SDE_AUX_MASK |
> SDE_TRANSB_FIFO_UNDER |
> - SDE_TRANSA_FIFO_UNDER;
> + SDE_TRANSA_FIFO_UNDER |
> + SDE_POISON;
> } else {
> mask = SDE_HOTPLUG_MASK_CPT |
> SDE_GMBUS_CPT |
> @@ -2272,7 +2282,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
> u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
> DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
> DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
> - DE_PIPEA_FIFO_UNDERRUN;
> + DE_PIPEA_FIFO_UNDERRUN | DE_POISON;
> u32 render_irqs;
>
> dev_priv->irq_mask = ~display_mask;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4d27320..62cfcea 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -520,6 +520,7 @@
>
> #define ERROR_GEN6 0x040a0
> #define GEN7_ERR_INT 0x44040
> +#define ERR_INT_POISON (1<<31)
> #define ERR_INT_MMIO_UNCLAIMED (1<<13)
> #define ERR_INT_FIFO_UNDERRUN_C (1<<6)
> #define ERR_INT_FIFO_UNDERRUN_B (1<<3)
> @@ -3569,6 +3570,7 @@
> #define SDEIER 0xc400c
>
> #define SERR_INT 0xc4040
> +#define SERR_INT_POISON (1<<31)
> #define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6)
> #define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3)
> #define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0)
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
