On Wed, Mar 27, 2013 at 6:24 PM, Jesse Barnes <jbarnes at virtuousgeek.org> wrote: > This looks good and seems to cover the bugs we've had here before. My > only concern is the one I mentioned before: on older chipsets we could > dither between plane, pipe, *and* port. Nowadays the pipe always does > it. > > So in the old LVDS case it would be cool if someone could test the > difference. The LVDS port may do a better job on 6bpc panels than the > pipe... I've considered this again, and it should fit neatly into the existing framework. If we want to use the dither on the lvds port on those platforms, but keep dithering on the pipe for e.g. DP we could switch lvds_compute_config to not clamp the bpp and then just enable the port dithering if config.pipe_bpp != 18. There's some further patches which unify this a bit, I guess we can discuss this a bit more once I resend them. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch
