Since 2514bc510d0c3aadcc5204056bb440fa36845147, the intel_dp_mode_fixup
function prefers lane count over frequency. That causes problems on
hardware that has less working lanes than it reports. This option allows
to workaround such hardware bugs.
Signed-off-by: Michal Srb <msrb at suse.com>
---
This is workaround for hardware issues uncovered by this commit:
commit 2514bc510d0c3aadcc5204056bb440fa36845147
Author: Jesse Barnes <jbarnes at virtuousgeek.org>
Date: Thu Jun 21 15:13:50 2012 -0700
drm/i915: prefer wide & slow to fast & narrow in DP configs
High frequency link configurations have the potential to cause trouble
with long and/or cheap cables, so prefer slow and wide configurations
instead. This patch has the potential to cause trouble for eDP
configurations that lie about available lanes, so if we run into that we
can make it conditional on eDP.
I have IBM POS machine (4852-570 Truman) that has internal monitor
connected over display port. It reports to have 2 lanes, but only 1
lane works reliably. With 2 lanes used, the monitor sometimes doesn't
turn on. It seems that this is hardware issue specific for this model.
>From discussion that was around the 2514bc510d0c3aadcc5204056bb440fa36845147
commit I understand there are more machines that have similar problems.
This option can be used to solve them.
---
drivers/gpu/drm/i915/i915_drv.c | 6 ++++++
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_dp.c | 15 +++++++++++++--
3 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6c4b13c..5949d7c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -123,6 +123,12 @@ module_param_named(preliminary_hw_support,
i915_preliminary_hw_support, int, 060
MODULE_PARM_DESC(preliminary_hw_support,
"Enable preliminary hardware support. (default: false)");
+int i915_dp_limit_max_lane_count __read_mostly = -1;
+module_param_named(dp_limit_max_lane_count, i915_dp_limit_max_lane_count,
int, 0600);
+MODULE_PARM_DESC(dp_limit_max_lane_count,
+ "Limit the maximal number of used display port lanes. "
+ "(default: -1 (no limit))");
+
static struct drm_driver driver;
extern int intel_agp_enabled;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1657d873..646e400 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1398,6 +1398,7 @@ extern int i915_enable_fbc __read_mostly;
extern bool i915_enable_hangcheck __read_mostly;
extern int i915_enable_ppgtt __read_mostly;
extern unsigned int i915_preliminary_hw_support __read_mostly;
+extern int i915_dp_limit_max_lane_count __read_mostly;
extern int i915_suspend(struct drm_device *dev, pm_message_t state);
extern int i915_resume(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 662a185..3812773 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -132,6 +132,17 @@ intel_edp_target_clock(struct intel_encoder
*intel_encoder,
return mode->clock;
}
+static inline u8
+intel_dp_max_lane_count(u8 dpcd[DP_RECEIVER_CAP_SIZE])
+{
+ u8 max_lane_count = drm_dp_max_lane_count(dpcd);
+
+ if(i915_dp_limit_max_lane_count != -1 && max_lane_count >
i915_dp_limit_max_lane_count)
+ max_lane_count = i915_dp_limit_max_lane_count;
+
+ return max_lane_count;
+}
+
static int
intel_dp_max_link_bw(struct intel_dp *intel_dp)
{
@@ -184,7 +195,7 @@ intel_dp_adjust_dithering(struct intel_dp *intel_dp,
{
int max_link_clock =
drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
- int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
+ int max_lanes = intel_dp_max_lane_count(intel_dp->dpcd);
int max_rate, mode_rate;
mode_rate = intel_dp_link_required(mode->clock, 24);
@@ -697,7 +708,7 @@ intel_dp_mode_fixup(struct drm_encoder *encoder,
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct intel_connector *intel_connector = intel_dp->attached_connector;
int lane_count, clock;
- int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
+ int max_lane_count = intel_dp_max_lane_count(intel_dp->dpcd);
int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
int bpp, mode_rate;
static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
--
1.7.7
