On Mon, Mar 25, 2013 at 07:36:51AM -0700, Jesse Barnes wrote:
> On Sat, 23 Mar 2013 17:46:31 -0700
> Ben Widawsky <ben at bwidawsk.net> wrote:
>
> > HSW doesn't overclock the same way as IVB or SNB. I do not know about
> > VLV, so I've kept that off as well. I'm still working on getting the doc
> > updates to explain how we overclock on Haswell.
> >
> > Cc: Jesse Barnes <jbarnes at virtuousgeek.org>
> > Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index ce3db2c..9c11dd9 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -2628,7 +2628,7 @@ static void gen6_enable_rps(struct drm_device *dev)
> > (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
> >
> > ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
> > - if (!ret) {
> > + if (!ret && IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
> > pcu_mbox = 0;
> > ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
> > if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
>
> This won't affect VLV, since I have a new rps enable function in my
> latest set. But it looks fine.
>
> Reviewed-by: Jesse Barnes <jbarnes at virtuousgeek.org>
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
