Hook up the LMEM region. Addresses will start from zero, and for CPU
access we get LMEM_BAR which is just a 1:1 mapping of said region.
Based on a patch from Michel Thierry.
Cc: Abdiel Janulgue <abdiel.janulgue@xxxxxxxxxxxxxxx>
Cc: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
Cc: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx>
Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
Signed-off-by: Matthew Auld <matthew.auld@xxxxxxxxx>
Signed-off-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_reg.h | 3 ++
drivers/gpu/drm/i915/intel_memory_region.c | 11 ++++++-
drivers/gpu/drm/i915/intel_region_lmem.c | 38 ++++++++++++++++++++++
drivers/gpu/drm/i915/intel_region_lmem.h | 2 ++
4 files changed, 53 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf9ba1e361bb..1af1966ac461 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -12063,6 +12063,9 @@ enum skl_power_gate {
#define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
+#define GEN12_LMEM_CFG_ADDR _MMIO(0xcf58)
+#define LMEM_ENABLE (1 << 31)
+
/* gamt regs */
#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c
index 67240bddf2ca..1f26bc06ec20 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -303,7 +303,16 @@ int intel_memory_regions_hw_probe(struct drm_i915_private *i915)
mem = i915_gem_stolen_setup(i915);
break;
case INTEL_MEMORY_LOCAL:
- mem = intel_setup_fake_lmem(i915);
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+ if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {
+ if (INTEL_GEN(i915) >= 9 && i915_selftest.live < 0 &&
+ i915->params.fake_lmem_start)
+ mem = intel_setup_fake_lmem(i915);
+ }
+#endif
+
+ if (IS_ERR(mem))
+ mem = i915_gem_setup_lmem(i915);
break;
}
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c b/drivers/gpu/drm/i915/intel_region_lmem.c
index 40d8f1a95df6..e98582c76de1 100644
--- a/drivers/gpu/drm/i915/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/intel_region_lmem.c
@@ -136,3 +136,41 @@ intel_setup_fake_lmem(struct drm_i915_private *i915)
return mem;
}
+
+static struct intel_memory_region *
+setup_lmem(struct drm_i915_private *dev_priv)
+{
+ struct pci_dev *pdev = dev_priv->drm.pdev;
+ struct intel_memory_region *mem;
+ resource_size_t io_start;
+ resource_size_t size;
+
+ /* Enables Local Memory functionality in GAM */
+ I915_WRITE(GEN12_LMEM_CFG_ADDR, I915_READ(GEN12_LMEM_CFG_ADDR) | LMEM_ENABLE);
+
+ io_start = pci_resource_start(pdev, 2);
+ size = pci_resource_len(pdev, 2);
+
+ mem = intel_memory_region_create(dev_priv,
+ 0,
+ size,
+ I915_GTT_PAGE_SIZE_4K,
+ io_start,
+ &intel_region_lmem_ops);
+ if (!IS_ERR(mem)) {
+ DRM_INFO("Intel graphics LMEM: %pR\n", &mem->region);
+ DRM_INFO("Intel graphics LMEM IO start: %llx\n",
+ (u64)mem->io_start);
+ DRM_INFO("Intel graphics LMEM size: %llx\n",
+ (u64)size);
+ }
+
+ return mem;
+}
+
+struct intel_memory_region *
+i915_gem_setup_lmem(struct drm_i915_private *i915)
+{
+ return setup_lmem(i915);
+}
+
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.h b/drivers/gpu/drm/i915/intel_region_lmem.h
index 213def7c7b8a..054e729035c1 100644
--- a/drivers/gpu/drm/i915/intel_region_lmem.h
+++ b/drivers/gpu/drm/i915/intel_region_lmem.h
@@ -10,6 +10,8 @@ struct drm_i915_private;
extern const struct intel_memory_region_ops intel_region_lmem_ops;
+struct intel_memory_region *i915_gem_setup_lmem(struct drm_i915_private *i915);
+
struct intel_memory_region *
intel_setup_fake_lmem(struct drm_i915_private *i915);
--
2.26.2
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