On Fri, Mar 01, 2013 at 01:14:11PM -0800, Jesse Barnes wrote:
> We don't generally use MI_FLUSH these days, but this bit may affect
> other flushing logic, so set it to be safe.
My earlier question stands. Why are we doing this only for VLV, when
the WA applies to everything since SNB?
>
> Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 1d5d613..e82b994 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -524,10 +524,14 @@ static int init_render_ring(struct intel_ring_buffer *ring)
> I915_WRITE(GFX_MODE,
> _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
>
> - if (IS_GEN7(dev))
> + if (IS_GEN7(dev)) {
> I915_WRITE(GFX_MODE_GEN7,
> _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
> _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
> + if (IS_VALLEYVIEW(dev))
> + I915_WRITE(MI_MODE, I915_READ(MI_MODE) |
> + _MASKED_BIT_ENABLE(MI_FLUSH_ENABLE));
> + }
>
> if (INTEL_INFO(dev)->gen >= 5) {
> ret = init_pipe_control(ring);
> --
> 1.7.9.5
>
> _______________________________________________
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> Intel-gfx at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrj?l?
Intel OTC
