On Thu, Oct 22, 2020 at 03:27:00PM -0700, Manasi Navare wrote:
> We create a new file for all VRR related helpers.
> Also add a function to check vrr capability based on
> platform support, DPCD bits and EDID monitor range.
>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Signed-off-by: Manasi Navare <manasi.d.navare@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_vrr.c | 28 ++++++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_vrr.h | 19 ++++++++++++++++
> 3 files changed, 48 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/display/intel_vrr.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_vrr.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index e5574e506a5c..3beeaf517191 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -249,6 +249,7 @@ i915-y += \
> display/intel_sdvo.o \
> display/intel_tv.o \
> display/intel_vdsc.o \
> + display/intel_vrr.o \
> display/vlv_dsi.o \
> display/vlv_dsi_pll.o
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> new file mode 100644
> index 000000000000..0c8a91fabb64
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -0,0 +1,28 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2020 Intel Corporation
> + *
> + * Author: Manasi Navare <manasi.d.navare@xxxxxxxxx>
> + */
> +
> +#include "i915_drv.h"
> +#include "intel_display_types.h"
> +#include "intel_vrr.h"
> +
> +bool intel_is_vrr_capable(struct drm_connector *connector)
> +{
> + struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
> + const struct drm_display_info *info = &connector->display_info;
> + struct drm_i915_private *dev_priv = to_i915(connector->dev);
> +
> + /*
> + * DP Sink is capable of Variable refresh video timings if
> + * Ignore MSA bit is set in DPCD.
> + * EDID monitor range also should be atleast 10 for reasonable
> + * Adaptive sync/ VRR end user experience.
> + */
> + return INTEL_GEN(dev_priv) >= 12 &&
> + drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) &&
> + info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
> +}
A whole new file for vrr seems overkill. There's probably
not going to be much to put in there.
> +
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
> new file mode 100644
> index 000000000000..755746c7525c
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2019 Intel Corporation
> +*/
> +
> +#ifndef __INTEL_VRR_H__
> +#define __INTEL_VRR_H__
> +
> +#include <linux/types.h>
> +
> +struct drm_connector;
> +struct drm_i915_private;
> +struct intel_crtc_state;
> +struct intel_encoder;
> +struct intel_dp;
> +
> +bool intel_is_vrr_capable(struct drm_connector *connector);
> +
> +#endif /* __INTEL_VRR_H__ */
> --
> 2.19.1
--
Ville Syrjälä
Intel
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