This allows us to use all 4 fdi lanes on fdi B when the cpu eDP is
running on pipe C. Yay!
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
---
drivers/gpu/drm/i915/intel_display.c | 16 +++++++++++-----
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 729c62a..58f1e35 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2289,10 +2289,15 @@ static void ivb_modeset_global_resources(struct drm_device *dev)
to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
uint32_t temp;
- /* When everything is off disable fdi C so that we could enable fdi B
- * with all lanes. XXX: This misses the case where a pipe is not using
- * any pch resources and so doesn't need any fdi lanes. */
- if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
+ /*
+ * When everything is off disable fdi C so that we could enable fdi B
+ * with all lanes. Note that we don't care about enabled pipes without
+ * an enabled pch encoder.
+ */
+ if (!(pipe_B_crtc->base.enabled &&
+ pipe_B_crtc->config.has_pch_encoder) &&
+ !(pipe_C_crtc->base.enabled &&
+ pipe_C_crtc->config.has_pch_encoder)) {
WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
@@ -3793,7 +3798,8 @@ static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
}
return true;
case PIPE_C:
- if (!pipe_B_crtc->base.enabled ||
+ if (!(pipe_B_crtc->base.enabled &&
+ pipe_B_crtc->config.has_pch_encoder) ||
pipe_B_crtc->config.fdi_lanes <= 2) {
if (pipe_config->fdi_lanes > 2) {
DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
--
1.7.11.4
