[PATCH] drm/i915: Fix and clean up RC6 init sequence for Haswell

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According to HSW PM Enabling guide, frequency bit was wrong.
Besides that, some setting values were different or not needed anymore on HSW.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
---
 drivers/gpu/drm/i915/i915_reg.h |   9 +++
 drivers/gpu/drm/i915/intel_pm.c | 121 ++++++++++++++++++++++++----------------
 2 files changed, 83 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e2b592a..b353c5b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4183,6 +4183,7 @@
 #define GEN6_RPNSWREQ				0xA008
 #define   GEN6_TURBO_DISABLE			(1<<31)
 #define   GEN6_FREQUENCY(x)			((x)<<25)
+#define   GEN7_FREQUENCY(x)			((x)<<24)
 #define   GEN6_OFFSET(x)			((x)<<19)
 #define   GEN6_AGGRESSIVE_TURBO			(0<<15)
 #define GEN6_RC_VIDEO_FREQ			0xA00C
@@ -4257,6 +4258,14 @@
 						 GEN6_PM_RP_DOWN_THRESHOLD | \
 						 GEN6_PM_RP_DOWN_TIMEOUT)
 
+#define  GEN7_PM_DEFERRED_EVENTS		(GEN6_PM_MBOX_EVENT | \
+						 GEN6_PM_THERMAL_EVENT | \
+						 GEN6_PM_RP_DOWN_TIMEOUT | \
+						 GEN6_PM_RP_UP_THRESHOLD | \
+						 GEN6_PM_RP_DOWN_THRESHOLD | \
+						 GEN6_PM_RP_UP_EI_EXPIRED | \
+						 GEN6_PM_RP_DOWN_EI_EXPIRED)
+
 #define GEN6_GT_GFX_RC6_LOCKED			0x138104
 #define GEN6_GT_GFX_RC6				0x138108
 #define GEN6_GT_GFX_RC6p			0x13810C
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f024e7d..cc81408 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2556,20 +2556,30 @@ static void gen6_enable_rps(struct drm_device *dev)
 	/* disable the counters and set deterministic thresholds */
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 
-	I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
-	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
-	I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
+	if (IS_HASWELL(dev))
+		I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
+	else {
+		I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
+		I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
+		I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
+	}
+
 	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
 	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
 
 	for_each_ring(ring, dev_priv, i)
 		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
 
-	I915_WRITE(GEN6_RC_SLEEP, 0);
-	I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
-	I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
-	I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
-	I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
+	if (IS_HASWELL(dev)) {
+		I915_WRITE(GEN6_RC_SLEEP, 0);
+		I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
+	} else {
+		I915_WRITE(GEN6_RC_SLEEP, 0);
+		I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
+		I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
+		I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
+		I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
+	}
 
 	/* Check if we are enabling RC6 */
 	rc6_mode = intel_enable_rc6(dev_priv->dev);
@@ -2595,12 +2605,19 @@ static void gen6_enable_rps(struct drm_device *dev)
 		   GEN6_RC_CTL_EI_MODE(1) |
 		   GEN6_RC_CTL_HW_ENABLE);
 
-	I915_WRITE(GEN6_RPNSWREQ,
-		   GEN6_FREQUENCY(10) |
-		   GEN6_OFFSET(0) |
-		   GEN6_AGGRESSIVE_TURBO);
-	I915_WRITE(GEN6_RC_VIDEO_FREQ,
-		   GEN6_FREQUENCY(12));
+	if (IS_HASWELL(dev)) {
+		I915_WRITE(GEN6_RPNSWREQ,
+			   GEN7_FREQUENCY(10));
+		I915_WRITE(GEN6_RC_VIDEO_FREQ,
+			   GEN7_FREQUENCY(12));
+	} else {
+		I915_WRITE(GEN6_RPNSWREQ,
+			   GEN6_FREQUENCY(10) |
+			   GEN6_OFFSET(0) |
+			   GEN6_AGGRESSIVE_TURBO);
+		I915_WRITE(GEN6_RC_VIDEO_FREQ,
+			   GEN6_FREQUENCY(12));
+	}
 
 	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
 	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
@@ -2621,41 +2638,51 @@ static void gen6_enable_rps(struct drm_device *dev)
 		   GEN6_RP_UP_BUSY_AVG |
 		   (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
 
-	ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
-	if (!ret) {
-		pcu_mbox = 0;
-		ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
-		if (ret && pcu_mbox & (1<<31)) { /* OC supported */
-			dev_priv->rps.max_delay = pcu_mbox & 0xff;
-			DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
-		}
+	if (IS_HASWELL(dev)) {
+		I915_WRITE(GEN6_PMIER, GEN7_PM_DEFERRED_EVENTS);
 	} else {
-		DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
-	}
-
-	gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
+		ret = sandybridge_pcode_write(dev_priv,
+					      GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
+					      0);
+		if (!ret) {
+			pcu_mbox = 0;
+			ret = sandybridge_pcode_read(dev_priv,
+						     GEN6_READ_OC_PARAMS,
+						     &pcu_mbox);
+			if (ret && pcu_mbox & (1<<31)) { /* OC supported */
+				dev_priv->rps.max_delay = pcu_mbox & 0xff;
+				DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
+			}
+		} else {
+			DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
+		}
 
-	/* requires MSI enabled */
-	I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
-	spin_lock_irq(&dev_priv->rps.lock);
-	WARN_ON(dev_priv->rps.pm_iir != 0);
-	I915_WRITE(GEN6_PMIMR, 0);
-	spin_unlock_irq(&dev_priv->rps.lock);
-	/* enable all PM interrupts */
-	I915_WRITE(GEN6_PMINTRMSK, 0);
-
-	rc6vids = 0;
-	ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
-	if (IS_GEN6(dev) && ret) {
-		DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
-	} else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
-		DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
-			  GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
-		rc6vids &= 0xffff00;
-		rc6vids |= GEN6_ENCODE_RC6_VID(450);
-		ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
-		if (ret)
-			DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
+		gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
+
+		/* requires MSI enabled */
+		I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
+		spin_lock_irq(&dev_priv->rps.lock);
+		WARN_ON(dev_priv->rps.pm_iir != 0);
+		I915_WRITE(GEN6_PMIMR, 0);
+		spin_unlock_irq(&dev_priv->rps.lock);
+		/* enable all PM interrupts */
+		I915_WRITE(GEN6_PMINTRMSK, 0);
+
+		rc6vids = 0;
+		ret = sandybridge_pcode_read(dev_priv,
+					     GEN6_PCODE_READ_RC6VIDS, &rc6vids);
+		if (IS_GEN6(dev) && ret) {
+			DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
+		} else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
+			DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
+					 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
+			rc6vids &= 0xffff00;
+			rc6vids |= GEN6_ENCODE_RC6_VID(450);
+			ret = sandybridge_pcode_write(
+				dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
+			if (ret)
+				DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
+		}
 	}
 
 	gen6_gt_force_wake_put(dev_priv);
-- 
1.7.11.7



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