On Thu, Feb 7, 2013 at 1:45 PM, Paulo Zanoni <przanoni at gmail.com> wrote: > 2013/2/6 Chris Wilson <chris at chris-wilson.co.uk>: >> Modifying the clock sources (via the DREF control on the PCH) is a slow >> multi-stage process as we need to let the clocks stabilise between each >> stage. If we are not actually changing the clock sources, then we can >> return early. >> >> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > > The patch looks correct, so: > Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com> > > But this patch only saves 400us. I thought this was on Daniel's "don't > care" range (e.g., on "drm/i915: don't send DP "idle" pattern before > "normal" on HSW PORT_A" I was asked to keep a potentially bigger delay > that's not needed at all). For modeset operations it's on my don't care list, since that'll take much longer anyway. But this tries to avoid it in boot-up, where fastboot aims to completely avoid the modeset. And I'm toying around with pushing all the edid reading to workqueues. So this could very much be in the "I care" bucket ;-) Hence also my proposal to simply push this into the modeset sequence instead of making the code more complicated ... -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch
